Circuit with diode-protected emitter resistors
AssigneeSGS-Thomson Microelectronics S.A.
InventorsFerdinando Lari, Pietro Erratico
Life of this patent
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Abstract
An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.
Claims36
An integrated circuit, comprising:
- first and second matched branches, each said branch including respective first and second transistors, both said first transistors having respective control terminals which are connected in common, and at least one said second transistor being connected to receive an input signal;
- each said first transistor having a second terminal thereof connected through a respective degeneration resistor to a node which is common to said first and second branches;
- wherein said degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type;
- and wherein said well region overlies a buried layer of said second conductivity type which is more heavily doped than said well region;
- and wherein said well region and said buried layer overlie a deeper region which is doped with said first conductivity type;
- and wherein said well region is laterally surrounded by a diffusion of said first conductivity type;
- and wherein no active devices are located in said well region with said resistors;
- and further comprising biasing circuitry connected to bias said first transistors at a level such that the junction between said first conductivity-type diffusion and said well region limits the voltage across said degeneration resistors and thereby prevents said transistors from going into saturation.
An integrated circuit, comprising:
- two matched bipolar transistors having respective bases thereof connected in common;
- each said transistor having an emitter thereof connected through a respective emitter degeneration resistor to a common node;
- wherein said degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type;
- and wherein said well region overlies a buried layer of said second conductivity type which is more heavily doped than said well region;
- and wherein said well region and said buried layer overlie a deeper region which is doped with said first conductivity type;
- and wherein said well region is laterally surrounded by a diffusion of said first conductivity type;
- and wherein no active devices are located in said well region with said resistors;
- and further comprising biasing circuitry connected to bias said bipolar transistors at a level such that the junction between said first conductivity-type diffusion and said well region limits the voltage across said degeneration resistors and thereby prevents said transistors from going into saturation.
An integrated circuit, comprising:
- first and second matched branches, each said branch including respective first and second transistors, both said first transistors having respective control terminals which are connected in common, and at least one said second transistor being connected to receive an input signal;
- each said first transistor having a second terminal thereof connected through a respective degeneration resistor to a node which is common to said first and second branches;
- wherein said degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type;
- and wherein no active devices are located in said well region with said resistors;
- and further comprising biasing circuitry connected to bias said first transistors at a level such that the junction between said first conductivity-type diffusion and said well region limits the voltage across said degeneration resistors and thereby prevents said transistors from going into saturation.
An integrated circuit, comprising:
- two matched bipolar transistors having respective bases thereof connected in common;
- each said transistor having an emitter thereof connected through a respective emitter degeneration resistor to a common node;
- wherein said degeneration resistors are each formed by a diffusion of first conductivity type within a shared monolithic semiconductor well region of a second conductivity type;
- and wherein no active devices are located in said well region with said resistors;
- and further comprising biasing circuitry connected to bias said bipolar transistors at a level such that the junction between said first conductivity-type diffusion and said well region limits the voltage across said degeneration resistors and thereby prevents said transistors from going into saturation.
An operational amplifier of a type which comprises a differential cell transconductor input stage incorporating a current mirror provided with a pair of degenerative resisters, and a gain stage driven directly by a transistor in said mirror, wherein each degenerative resistor is implemented within an epitaxial well wherewith a parasitic diode is associated, and each said diode is connected in parallel with a corresponding one of said resisters.
Dependencies are inferred from the claim text.