Non-volatile memory
AssigneeSharp Kabushiki Kaisha
InventorsYoshimitsu Yamauchi, Kenichi Tanaka, Keizo Sakiyama
Life of this patent
Estimating the term…
Abstract
A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them. The non-volatile memory further includes a programmable insulating film provided in self-alignment between the gate electrode and at least one of the source and drain diffusion layers and the programmable insulating film is broken down by a voltage applied to the gate electrode so as to execute programming.
Claims8
A non-volatile memory cell of which includes a single MOS transistor, comprising:
- a semiconductor substrate;
- source and drain diffusion layers and a channel region between said source and diffusion layers formed on a surface of said semiconductor substrate;
- a gate electrode disposed over said semiconductor substrate with a gate insulating film interposed between said gate electrode and said channel region;
- and
- a programmable insulating film provided in self-alignment between said gate electrode and either one of said source and drain diffusion layers so that said programmable insulating film is selectively broken down by a predetermined voltage applied to said gate electrode to execute programming and electrically conduct between said gate electrode and either one of said source and drain diffusion layers, and a breakdown voltage of said gate insulating film is higher than that of said programmable insulating film and said predetermined voltage;
- said gate insulating film and said programmable insulating film disposed adjacent to each other under said gate electrode.
A non-volatile memory cell of which includes a single MOS transistor, comprising:
- a semiconductor substrate;
- source and drain diffusion layers and a channel region between said source and drain diffusion layers formed on a surface of said semiconductor substrate;
- a gate electrode disposed over said semiconductor substrate with a gate insulating film interposed between said gate electrode and said channel region;
- and
- a programmable insulating film provided in self-alignment between said gate electrode and either one of said source and drain diffusion layers and between said gate electrode and a polysilicon spacer in ohmic contact with at least one of said source and drain diffusion layers and on a side wall of said gate electrode so that said programmable insulating film is selectively broken down by a voltage applied to said gate electrode to execute programming and electrically conduct between said gate electrode and either one of said source and drain diffusion layers, and a breakdown voltage of said programmable insulating film is smaller than that of said gate insulating film.
Dependencies are inferred from the claim text.