Method of fabricating high voltage junction termination extension structure for a semiconductor integrated circuit device

A method of fabricating a junction terminal extension structure for a high-voltage integrated circuit device having an anode and a cathode comprising the steps of:

• forming a first protective layer over a silicon substrate and patterning the first protective layer to expose a location on the silicon substrate between the anode and the cathode:
• forming a first layer of silicon oxide at said location on the silicon substrate;
• forming a second protective layer over the silicon substrate and patterning the second protective layer to expose most of the silicon oxide, wherein a portion of the silicon oxide proximate the anode of the high-voltage integrated circuit device is also covered with said second protective layer;
• forming a second field oxide layer on said first layer where not protected by said second protective layer;
• removing the first and second protective layers, said first and second layers of silicon oxide defining a stepped field oxide layer in the proximity of the anode of said high-voltage integrated circuit device;
• forming an anode metal layer at said anode, and forming a field region plate extending from said anode metal layer over the stepped field oxide layer;
• forming a third oxide layer over said substrate and patterning to define at least a cathode lead opening therein;
• and
• forming a cathode metal layer at said cathode and a high-voltage metal interconnection extending from said cathode metal layer and over said first, second and third oxide layers to provide said junction terminal extension structure of said high-voltage integrated circuit.