Method of forming a bit line over capacitor array of memory cells

A method of forming a bit line over capacitor array of memory cells comprising the following steps:

• providing rant array of substantially electrically isolated word lines atop a semiconductor wafer;
• providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line;
• providing a layer of electrically insulating material over the word lines and active areas, the layer of insulating material having an upper surface which is above the word lines;
• providing first and second respective contact openings through the insulating material layer to the respective first and second active regions;
• providing electrically conductive material within the first and second contact openings which electrically connects with the respective first and second active regions, the electrically conductive material within the respective first and second contact openings collectively extending elevationally over and above the insulating material upper surface, the electrically conductive material within the first contact openings electrically connecting with the electrically conductive material of the second contact openings above the insulating material upper surface;
• and
• in a single step, chemical-mechanical polishing the collective electrically conductive material extending over and above the insulating material upper surface downwardly to at least the upper surface of the insulating material, the single chemical-mechanical polishing step effectively electrically isolating the conductive material within the first contact openings from the conductive material within the second contact openings.