Method for controlling solder bump height for flip chip integrated circuit devices

A method for controlling the height of input/output solder bumps which electrically interconnect a flip chip device to a substrate, the method comprising the steps of:

• forming non-input/output solder bumps and said input/output solder bumps on a surface of said flip chip device, said input/output solder bumps defining terminal locations on said flip chip device;
• forming a flip chip conductor pattern on said substrate which is complementary to said terminal locations on said flip chip device, said flip chip conductor pattern comprising a plurality of conductor pads on said substrate;
• forming non-input/output pads on said substrate for mating with said non-input/output solder bumps;
• mating said flip chip device with said substrate such that said terminal locations register with said flip chip conductor pattern so as to electrically interconnect said input/output solder bumps to said plurality of conductor pads, and such that said non-input/output solder bumps register with said non-input/output pads;
• and
• reflow soldering said flip chip device to said substrate such that the height of each of said non-input/output solder bumps is determined by the composition and size of a corresponding one of said non-input/output pads, a sufficient number of said non-input/output solder bumps being present such that a buoyant force generated by said non-input/output solder bumps balances an opposing tensional force generated by the surface tension of said input/output solder bumps during said reflow soldering step;
• whereby the height of each of said input/output solder bumps is substantially dictated by the height of said non-input/output solder bumps.