Circuit board for high pin count surface mount pin grid arrays

A method of soldering a surface mount pin grid array integrated circuit package having a plurality of pins arrayed in a pattern to a first surface of a printed circuit board having a plurality of conductive pads arrayed thereon in a mating pattern, said method comprising the steps of:

• a. placing a first solder mask layer on the first surface of the printed circuit board;
• b. patterning said first solder mask layer to expose the pads;
• c. placing a second solder mask layer over said first solder mask layer;
• d. patterning said second solder mask layer to expose the pads;
• e. placing a third solder mask layer over said second solder mask layer;
• f. patterning said third solder mask layer to expose the pads;
• g. limiting the total thickness of the combined first solder mask layer, second solder mask layer and third solder mask layer to a range of between 4 and 12 mils;
• h. masking the pads;
• i. hot-air solder levelling the printed circuit board;
• j. unmasking the pads;
• k. coating the pads with an anti-tarnish agent;
• l. placing a predetermined amount of solder paste over each pad in wells formed thereover by said first solder mask, said second solder mask and said third solder mask;
• m. placing the surface mount pin grid array integrated circuit package pins into their respective wells of the printed circuit board to form a pre-solder assembly;
• n. applying a downward pressure on the surface mount pin grid array integrated circuit package with respect to the printed circuit board;
• o. heating said pre-solder assembly to a temperature sufficient to melt said solder paste to form a post-solder assembly;
• and
• p. cooling said post-solder assembly.