Matrix type surface pressure distribution detecting element

An integrated circuit semiconductor device comprising a surface pressure distribution matrix of detecting elements, said device comprising a plurality of transistors arranged in a matrix form on a p-type semiconductor substrate, said integrated circuit comprising an n+-type buried layer in the p-type semiconductor substrate, an n-type epitaxial layer over said n+-type buried layer, a p-type isolation layer of said substrate separating crosspoints, a p-type base layer and an n-type emitter layer over said n-type epitaxial layer, a silicon oxide film over an upper surface of said substrate and said layers in said substrate, the parts of the silicon oxide film which are over the p-type base layer and the n-type emitter layer, base electrodes and emitter electrodes being in contact with said base and emitter layers respectively, and a protective insulating film completely covering all of the structure except for exposing the emitter electrodes,

• said emitter electrodes being contact terminals arranged in rows and columns and being exposed above said substrate in said matrix form,
• second electrodes on each of said transistors arranged in rows on said semiconductor substrate, each of the second electrodes in a row being commonly connected to each other,
• each of said rows being electrically isolated from other of said rows of electrodes,
• a third electrode on each of said transistors, said third electrodes being arranged in columns perpendicular to said rows, the third electrodes in each column being commonly connected to each other,
• each of said columns being electrically isolated from other of said columns,
• each emitter electrode which receives a surface pressure causing a transistor to be turned on at the location where pressure is applied to one of said emitter electrodes whereby a pattern of turned on transistors corresponds to a pattern of applied pressure.

An integrated circuit semiconductor surface pressure distribution matrix detector comprising a plurality of transistors arranged in a matrix form on a p-type semiconductor substrate, an n+-type buried layer in the p-type semiconductor substrate, an n-type epitaxial layer over said n+-type buried layer, a p-type isolation layer of said substrate separating said crosspoints, a p-type base layer and an n-type emitter layer over said n-type epitaxial layer, a silicon oxide film over an upper surface of said substrate and said layers in said substrate, the parts of the silicon oxide film which are over the p-type base layer and the n-type emitter layer, base electrodes and emitter electrodes being in contact with said base and emitter layers respectively, and a protective insulating film completely covering all of the structure except for a window exposing the emitter electrodes,

• said emitter electrodes being contact terminals arranged in rows and columns, and being arranged in said matrix form,
• a collector electrode on each of said transistors, said transistors being arranged in rows and columns on said semiconductor substrate with said collector electrodes being commonly connected in columns and with electrical isolation between said columns,
• a base electrode on each of said transistors, said base electrodes being commonly connected in rows with electrical isolation between said rows,
• a surface pressure upon at least some area on at least one of said emitter electrodes causing a transistor at the pressure location to be turned on via its emitter electrode.

An integrated circuit semiconductor device for detecting a surface pressure distribution matrix detector comprising a plurality of field effect transistors formed in a matrix on an n-type semiconductor substrate, a p-type well layer in said n-type silicon substrate, a gate oxide film formed in and a gate polysilicon film formed on said well layer, phosphorus ions implanted into a resultant structure by using the gate polysilicon film as a mask to provide drain and source layers in said well layer, an insulating interlayer covering the gate polysilicon film,

• a drain electrode contact window in the insulating interlayer, a drain electrode wiring layer commonly interconnecting drains to define columns of drains in said matrix crosspoints,
• an insulating protective film of polyamide over said substrate and structures formed thereon, a contact window in said insulating protective film over each source electrode of transistors in said matrix, said source electrodes being contact terminals having resistance to corrosion,
• one of said source and drain electrodes on each of said transistors being exposed above said substrate and providing a pressure detecting element, said one of said source and drain electrodes being arranged in said matrix form,
• one of said source and drain electrodes being an electrode to be touched by an applied pressure,
• the other of said source and drain electrodes on each of said transistors being arranged in rows on said semiconductor substrate, each of said other of said source and drain electrodes in a row being commonly connected to each of the other of said source and drain electrodes in that row, each of said rows being electrically isolated from other of said rows of electrodes,
• said gate polysilicon film forming gate electrodes on each of said transistors arranged in said columns perpendicular to said rows,
• each of said columns being electrically isolated from other of said columns,
• a surface pressure making contact with at least one of said one of the source and drain electrodes in order to cause at least one transistor to be turned on at the location where said one of the source and drain electrode is touched by said flexible film.

An integrated circuit semiconductor surface pressure distribution matrix detector comprising a plurality of field effect transistors formed in a matrix on an n-type semiconductor substrate, a p-type well layer in said n-type silicon substrate, a gate oxide film formed in and a gate polysilicon film formed on said well layer, phosphorus ions implanted into a resultant structure by using the gate polysilicon film as a mask to provide drain and source layers in said well layer, an insulating interlayer covering the gate polysilicon film,

• a drain electrode contact window in the insulating interlayer, a drain electrode wiring layer commonly interconnecting drains to define rows of drains in said matrix crosspoints,
• an insulating protective film over said substrate and structures formed thereon, a contact window in said insulating protective film over each source electrode of transistors in said matrix, said source electrodes being contact terminals having resistance to corrosion, a source electrode on each of said transistors being exposed above said substrate and providing a pressure detecting element, said source electrodes being arranged in said matrix form,
• said drain electrodes on said transistors being arranged in said rows on said semiconductor substrate with each of said rows being electrically isolated from other of said rows of electrodes,
• said gate electrodes being arranged in columns perpendicular to said rows, each of said columns being electrically isolated from other of said columns,
• a surface pressure making some degree of contact with at least one of said source electrodes, said degree of contact corresponding to a degree of applied pressure in order to cause at least one transistor to be turned on at the location where said source electrode is touched.