All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging

A method for adjusting the phase of a reference clock to track incoming received serial data including a method for analyzing the edge position of binary transitions in said received serial data with respect to said reference clock and determining the average edge position of said received serial data, comprising:

• a. initiating a time ruler pulse train upon arrival of transitions of said received serial data by launching a pulse into a serially connected plurality of unit delay elements, each said unit delay element having an input terminal, an intermediate terminal and an output terminal;
• b. connecting the input, intermediate and output terminals of said unit delays into an edge distribution analyzer circuit for sampling and analyzing said pulse train;
• c. sampling the signal at each said input, intermediate and output terminal at the occurrence of a selected transition of said reference clock;
• d. combinatorially interconnecting said sampled signals and said reference clock to provide a running early versus late difference count of the difference between the number of receiver data transitions which are early (E) versus late (L) with respect to said selected transition of said reference clock;
• and
• e. analyzing said early versus late difference count to generate a correction signal for adjusting the phase of said reference clock to drive said early minus late (E-L) difference count toward zero,
• wherein said step of combinatorially interconnecting also provide a running count of the difference between the number of receiver data transitions, I, which are earlier than a first predetermined time and the number of receiver data transition, O, which are later than a second predetermined time, said difference being called I-O difference count;
• and
• analyzing said I-O difference count to generate a correction signal for adjusting the phase of said reference clock to drive said I-O difference count toward a positive maximum value.

An all digital phase lock loop comprising:

• means for sampling the transition edge positions of incoming serial binary data, said incoming serial binary data transition edge positions being derived from a distant clock;
• means for generating a broadband time ruler signal;
• means for adjustably shifting the phase of said broadband time ruler signal;
• means for comparing said shifted broadband time ruler signals to said edge positions of said incoming serial binary data and analyzing the results of said comparison, said means for adjustably shifting said broadband time ruler signal being responsive to said analyzed comparison, wherein said means for comparing provides a statistically averaged transition edge position and said means for adjustably shifting causes the said phase of said broadband time ruler signal to track said statistically averaged transition edge position;
• and
• wherein said means for generating a broadband time ruler signal includes;
• means for causing said broadband time ruler to have a spectrum containing at least a first and second base frequency, the first said base frequency being the frequency corresponding to the period of a local reference clock multiplied by N, where N is the number of pulses in the compensated broadband time ruler;
• and wherein the said second base frequency corresponds to the period equal to T.sub.1 +T.sub.2, where T.sub.1 =1/F.sub.R and T.sub.2 =1/F.sub.R -F.sub.T, where F.sub.R equals the frequency of local reference clock and F.sub.T equals the frequency of said distant clock.

In a binary data receiver apparatus for decoding an incoming serial binary data stream wherein said incoming serial binary data is a two level voltage pulse stream having transitions which are derived from a remote oscillator output signal, said remote oscillator output signal having a specified fixed frequency and tolerance and wherein said apparatus for decoding further includes terminal means for receiving a signal from a local reference oscillator signal derived in said binary data receiver apparatus, said local reference oscillator signal being of the same specified fixed frequency and tolerance as said remote oscillator, said local reference oscillator signal being asynchronously related to said remote oscillator output,

• the improvement comprising,
• a digitally variable delay line having outputs;
• means for providing a bit clock signal, said bit clock signal having a broadband frequency including a first frequency equal to a multiple of said local reference oscillator signal and a second frequency derived from said delay line outputs, said means for providing a bit clock signal includes means for launching a pulse into said digitally variable delay line once per cycle of said local reference oscillator, said delay line outputs being multiple, displaced output tap terminals, whereby said launched pulse signal propagates in said delay line and whereby signals appear at each of said multiple, displaced delay line output tap terminals and where each said tap terminal signal is a different phase shifted copy of said launched pulse which had been launched into said delay line, and where the time delay between each said tap terminals is equal;
• means for sampling the transition edge positions of said transitions of said incoming serial binary data stream;
• means for digitally analyzing said transition edge positions to determine the average edge position of said incoming serial binary data stream by comparing said transition edge position to the phase of a shifted version of said bit clock signal, and
• means for providing digital command signals to select a different phase of said bit clock signal to reduce the phase difference between said incoming serial binary data stream and said bit clock signal.