Fram aligner with reduced circuit scale

An alignment circuit for aligning frames of serial data that have been demultiplexed to units of a certain number of bits of parallel input data, comprising:

• a shift register for storing two of said units of said parallel input data;
• a data scanner coupled said shift register, for testing all bits in said shift register except for one bit in said shift register, detecting a unit having a certain first value, and when such a unit is detected, generating alignment data indicating a position in said shift register where said unit was detected;
• a logic circuit coupled to said data scanner, for determining, from said alignment data, whether a unit having said first value has been detected, and generating a first sync unit detect signal;
• a latch coupled to said logic circuit, for latching said alignment data responsive to said first sync unit detect signal and an enable signal;
• a first data comparator coupled to said latch, for comparing alignment data output from said data scanner with alignment data latched in said latch, counting consecutive occurrences of said first sync unit detect signal, and generating an alignment match signal when said first sync unit detect signal has been received a certain number of times consecutively and said alignment data output from said data scanner match said alignment data latched in said latch;
• an aligner coupled to said shift register, for extracting a unit of data from said shift register according to the alignment data latched in said latch;
• a second data comparator coupled to compare the unit of data extracted by said aligner with a certain second value and generate a second sync unit detect signal when they match;
• and
• a sync pattern detector coupled to receive said alignment match signal and said second sync unit detect signal and generate a sync detect signal when said alignment match signal is followed consecutively by a certain number of second sync unit detect signals.