Apparatus and method for synchronizing an input data stream with bit or phase synchronization

A synchronizing device to synchronize a digital input data signal (Din) with a digital clock signal (CK), said digital input data signal (Din) being rate synchronous with said digital clock signal (CK), said device including

• a sampling means (S) to sample said digital input data signal (Din);
• a grouping means (ST) to group the samples obtained by said sampling means in successive sets each comprising a plurality of successive ones of said samples;
• a detection means (D) to detect in each of said successive sets possible value transitions of said samples;
• and
• a processing means (SD, M, GE) to process said value transitions, under the control of said digital clock signal to produce an output signal (Dout) which is the digital input signal (Din) synchronized with said digital clock signal (CK),
• said processing means (P) includes a position determining means (SD) to determine for each current value transition detected in said successive sets of a theoretical current position (STC) in said successive sets of samples assumed to be obtained by sampling a theoretical nominal input data signal and also includes a generation means (GE) to generate said output signal (Dout) using said theoretical current position (STC) and an end value (TS) of said current value transition.

A synchronizing device to synchronize a digital input data signal (Din) with a digital clock signal (CK), said digital input data signal (Din) being rate synchronous with said digital clock signal (CK), said device including

• sampling means (S) to sample said digital input data signal (Din);
• grouping means (ST) to group the samples obtained by said sampling means in successive sets each comprising a plurality of successive ones of said samples;
• detection means (D) to detect in each of said successive sets possible value transitions of said samples;
• processing means (SD, M, GE) to process said value transitions, under the control of said digital clock signal (CK), to produce an output signal (Dout) which is the digital input signal (Din) synchronized with said digital clock signal (CK);
• said processing means (P) includes a position determining means (SD) to determine for each current value transition detected in said successive sets of a theoretical current position (STC) in said successive sets of samples assumed to be obtained by sampling a theoretical nominal input data signal and also includes a generation means (GE) to generate said output signal (Dout) using said theoretical current position (STC) and an end value (TS) of said current value transition;
• each of said sets comprises two subsets of equal numbers of samples, each subset comprising a group of four samples obtained by said sampling and an additional sample equal to the last sample of a previous subset;
• and
• said real current position of said current value transition in said set is determined by one position (PC) of the subset to which said transition belongs in said set, and another position (ELC) of said current value transition in said subset to which said current value transition belongs.