Isk receiver
AssigneeMitel Corporation
InventorAlexander F. Tulai
Life of this patent
Estimating the term…
Abstract
A class message receiver that in one embodiment can be implemented in a Digital Signal Processor. An FSK demodulator takes input linear samples of the signal and filters them with a bandpass filter which does an upsampling to increase the sampling rate from 8,000 Hz to 24,000 Hz, which results in 20 samples at the output of the bandpass filter for each incoming data bit. The amplitude of the signal/samples at the output of the bandpass filter is adjusted by an automatic gain control (AGC) circuit and the resulting samples (for convenience referred as sample (t), where t is a discrete moment in time) are processed along two different paths designed to estimate the likelihood of the input signal encoding a mark (mark estimation path) or a space (space estimation path).
Claims19
A frequency shift keyed receiver comprising:
- (a) means for receiving a demodulated frequency shift keyed sampled sequence of data bits which is frequency shift keyed by upper and lower frequencies .omega..sub.s and .omega..sub.m,
- (b) means for encoding the received sequence with pairs of 90.degree. phase shifted signals of upper frequency .omega..sub.s of said frequency shift keyed sampled sequence and lower frequency .omega..sub.m of said frequency shift keyed sampled sequence resulting in a pair of mutually 90.degree. phase shifted sampled sequence signals encoded by .omega..sub.s and a pair of mutually 90.degree. phase shifted sampled sequence signals encoded by .omega..sub.m,
- (c) a pair of most likely (ML) estimators each for receiving a corresponding pair of phase shifted sampled sequence signals and for continuously operating on said pairs of phase shifted sampled sequence signals to obtain a pair of output signals one representing the likelihood of the upper frequency and one representing the likelihood of the lower frequency sequence having a data bit present,
- (d) a baud recovery circuit for determining the timing of a mark or space bit and for providing an enable signal corresponding to the timing thereof,
- (e) a slicer for receiving said output signals and the enable signal and providing amplitude levels of the output signals at an input to a decision circuit when enabled,
- (f) said decision circuit indicating the higher amplitude one of said output signals.
A frequency shift keyed receiver comprising:
- (a) means for receiving a demodulated frequency shift keyed sampled sequence of mark and space data bits,
- (b) means for separately operating on 90.degree. phase shifted pairs of said data bits by a process ##EQU5## in which .omega..sub.i is .omega..sub.m and .omega..sub.s in separate operations, to provide a pair of mark and space estimated signals, wherein .omega..sub.m is a lower frequency and .omega..sub.s is an upper frequency,
- (d) means for low pass filtering one of said mark and space estimated signals,
- (e) means for differentiating said one signal to obtain a slicer enable signal at the times when the slope of the low pass filtered said one signal changes from a positive to a 0 slope prior to changing to a negative slope,
- (f) slicer means for receiving said estimated signals, and for receiving said enable signal, whereby a slice of said estimated signals at the time of said enable signal is provided at an output,
- (g) a decision circuit for receiving said slice of said estimated signals, for determining which of the estimated signals is the greater and for providing an indication of the presence of a mark or space bit thereby.
Dependencies are inferred from the claim text.