Semiconductor device with function of testing insulation defect between bit lines and testing method therefor

A semiconductor device comprising:

• a memory cell matrix having a plurality of memory cells arranged in a matrix form;
• a group of bit lines connected to said memory cells and provided for respective columns of said memory cell array;
• a testing circuit for effecting the test to check whether said memory cell matrix correctly functions or not;
• first potential supplying means contained in said testing circuit and having input and output terminals, said input terminal being supplied with a signal for commanding the start of the test and said output terminal being connected to even-numbered bit lines in said bit line group, for supplying a first potential to said even-numbered bit lines according to said signal;
• and
• second potential supplying means contained in said testing circuit and having input and output terminals, said input terminal being supplied with said signal and said output terminal being connected to odd-numbered bit lines in said bit line group, for supplying a second potential having a potential level different from the potential level of the first potential to said odd-numbered bit lines according to said signal.

A testing method for semiconductor devices, comprising the steps of:

• supplying a first potential to even-numbered bit lines among bit lines constructing a bit line group;
• supplying a second potential having a potential level different from the potential level of said first potential to odd-numbered bit lines among said bit lines constructing said bit line group with said first potential kept supplied to said even-numbered bit lines;
• and
• causing an electrical stress between bit lines by supplying said first potential to said even-numbered bit lines and supplying said second potential to said odd-numbered bit lines.

A semiconductor device comprising:

• first supplying means for supplying a first potential to even-numbered bit lines among bit lines constructing a bit line group;
• second potential supplying means for supplying a second potential having a potential level different from the potential level of said first potential to odd-numbered wiring layers among said bit lines constructing said bit line group;
• and
• a testing circuit containing said first and second supplying means, for causing an electrical stress between said bit lines by causing said first potential to be supplied to said even-numbered bit lines and causing said second potential to be supplied to said odd-numbered bit lines.