Apparatus and method for defective column detection for semiconductor memories

A method of screening an integrated circuit for memory column charge leakage characteristics, said integrated circuit having an array of rows and columns of non-volatile memory cells, said method comprising the steps of:

• applying a potential to the rows of said array of non-volatile memory cells;
• selectively coupling at least one of said columns of said array of non-volatile memory cells through a silicon implemented analog multiplexer to an output pad on said integrated circuit;
• and
• measuring the output current at said output pad to determine if a selected column exhibits charge leakage characteristics by having a current above an allowable threshold.

A method for stressing a non-volatile memory array, having a plurality of rows and columns on an integrated circuit comprising the steps of:

• applying a potential substantially greater than the operating voltage of the integrated circuit to a high-voltage capable pad of the integrated circuit;
• selectively coupling electrically said pad through an on-chip analog multiplexer to the desired columns of said non-volatile memory array;
• and
• holding said potential across said desired columns of said non-volatile memory array for a predetermined period of time, thereby stressing said non-volatile memory array.