Semiconductor integrated circuit device and semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsuya Matsumura, Satoshi Kumaki, Shinichi Nakagawa
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Abstract
In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.
Claims7
A semiconductor integrated circuit device having a data latch function, comprising:
- data accept means responsive to a clock signal for accepting externally applied data;
- first and second switching means each including a control electrode, one electrode and the other electrode, responsive to the data accepted by said data accept means for being turned on/off in a complementary manner;
- an inverter having its input node commonly connected to the one electrodes of said first and second switching means, and its output node connected to the control electrodes of said first and second switching means;
- and
- a set/reset terminal for providing plural signals for setting/resetting the data latch function to the other electrodes of said first and second switching means.
A semiconductor integrated circuit device having a data latch function, comprising:
- data accept means responsive to a clock signal for accepting externally applied data;
- first and second switching means each including a control electrode, one electrode, and the other electrode responsive to the data accepted by said data accept means for being turned on/off in a complementary manner;
- an inverter having an input node commonly connected to the one electrodes of said first and second switching means, and an output node connected to a data output terminal;
- third switching means responsive to said clock signal for turning on/off the region between the output node of said inverter and the control electrodes of said first and second switching means, and
- a set/reset terminal for applying a signal for setting/resetting the data latch function to the other electrode of said first or second switching means.
A semiconductor integrated circuit device having a data latch function, comprising:
- data accept means responsive to a clock signal for accepting externally applied data;
- a latch circuit consisting of
- a) first and second switching means each including a control electrode, first electrode and second electrode, responsive to the data accepted by said data accept means for being turned on/off in a complementary manner, and
- b) an inverter having its input node commonly connected to the first electrodes of said first and second switching means, and its output node connected to the control electrodes of said first and second switching means;
- and
- a set/reset terminal for providing plural signals to the second electrodes of said first and second switching means for setting/resetting the latch circuit.
Dependencies are inferred from the claim text.