Semiconductor memory device with changeable input/output data bit arrangement

A method of driving a semiconductor memory device including a memory cell array having a plurality of memory cells and a plurality of data input nodes, said method comprising the steps of:

• generating a pin selecting signal indicating whether each of said data input nodes is available,
• selecting simultaneously a number of memory cells corresponding in number to said data input nodes from said memory cell array, each of the selected plurality of memory cells corresponding to a different data input node,
• writing data applied to an input node indicated available into a corresponding memory cell according to said pin selecting signal,
• generating a switching signal indicating that a different input node differing from said data input nodes is to be used,
• generating a block selecting signal to select a memory cell out of said selected memory cells to which data applied to said different input node is to be written in response to said switching signal, and
• invalidating said pin selecting signal for writing data of a logic corresponding to the data applied to said different input pin according to said block selecting signal into a memory cell specified by said block selecting signal.

A method of driving a semiconductor memory device including a memory cell array having a plurality of memory cells and a plurality of data output nodes, said method comprising the steps of:

• generating pin selecting signals indicating whether each of said data output nodes is available,
• selecting simultaneously a number of memory cells corresponding in number to said data input nodes from said memory cell array, each of the selected memory cells corresponding to a different data output node,
• providing data read out from a memory cell corresponding to an output node indicated available to the indicated available output node according to said pin selecting signals,
• generating a switching signal for carrying out data output using only a specific output node out of said data output nodes,
• generating a block selecting signal for specifying a memory cell corresponding to said specific output node out of said selected memory cells, and
• providing to said specific output node the data of a memory cell specified by said block selecting signal in response to said switching signal and said block selecting signal.