Semiconductor memory chip

A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising:

• a write address input port including a single lead for serially receiving a start write address for a sequence of memory access operations;
• a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses commencing with the start write address, which are applied to the decoder, sequential ones of the memory write addresses being incremented from the prior memory write address by an offset value;
• and
• a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer.

A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising:

• a write address input port including a single lead for serially receiving a start write address for a sequence of memory access operations;
• a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses, commencing with the start write address, which are applied to the decoder, the write address sequencer being arranged to increment sequential ones of the memory write addresses by a variable offset value;
• a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer;
• a read address input port including a single lead for serially receiving a start read address for a sequence of memory access operations;
• a read address sequencer, connected to the read address input port and responsive to the start read address and a second clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder, the read address sequencer being arranged to increment sequential ones of the memory read addresses by a variable offset value;
• and
• a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.

A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising:

• a read address input port including a single lead for serially receiving bits of a start read address for a sequence of memory access operations;
• a read address sequencer, connected to the read address input port and responsive to the start read address and a clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder;
• and
• a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.