US 5,400,285 A · Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device includes a sense amplifier for amplifying the data stored in a memory cell, activated in accordance with a binary output enable signal fed to the integrated circuit device, in order to reduce the power consumption thereof. When the output enable signal is at a first level, in which the output of the integrated circuit device becomes in a floating state after a memory cell is selected to be read out, the sense amplifier is disabled to reduce the power consumption. The sense amplifier is disabled in response to a signal from a control circuit, which produces a logical output signal based on output enable signal and a control signal used to activate the sense amplifier only for the read operation. While the sense amplifier is temporarily disabled, the output of the sense amplifier is latched by a latch circuit, which is also controlled by the output enable signal, to guarantee an output enable access time.

Claims19

Dependent claims

A semiconductor integrated circuit device, an output of the device being in a floating state in response to an output enable signal fed to the device, the device comprising:

a plurality of word-lines;
a plurality of bit-line pairs, disposed so as to intersect said word-lines;
a plurality of memory cells, each connected to one of said word-lines and to one of said bit-line pairs;
a sense amplifier having an active state and an inactive state, said sense amplifier being connected to a selected one of said bit-line pairs, said sense amplifier amplifying a voltage difference between the bit-lines of the selected bit-line pair when said sense amplifier is in the active state;
and
a logic circuit, responsive to a control signal and the output enable signal, for providing a logic signal that controls said sense amplifier to be in the active state and the inactive state.

3 more elements

A method of performing read operations and write operations in a semiconductor integrated circuit device, the device including a plurality of word-lines, a plurality of bit-line pairs, disposed so as to intersect the word-lines, a plurality of memory cells, each connected to one of the word-lines and to one of the bit-line pairs, a sense amplifier, selectively activatable by connection to one of the bit-line pairs, for amplifying a voltage difference between the bit-lines of the one of the bit-line pairs during the read operations, and a device output having a floating state when and only when an output enable signal, having alternative first and second output enable levels, is applied to the device at the first output enable level, the method comprising the steps of:

a. applying the output enable signal at the first output enable level, to the device, during first selected time periods of the read operations;
b. applying the output enable signal at the second output enable level, to the device, during time periods other than the first selected time periods;
c. providing the device output in the floating state only while the output enable signal is applied to the device at the first output enable level;
d. providing a control signal having at different times, respectively a first control level and a second control level;
and
e. activating the sense amplifier when, and only when the control signal has the first control level and the output enable signal has the second output enable level.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device

Life of this patent

Semiconductor integrated circuit device

Life of this patent

Abstract

Claims19