Nonvolatile semiconductor memory device with NAND cell structure

An electrically erasable programmable semiconductor memory device comprising:

• a semiconductive substrate;
• parallel bit lines provided above said substrate;
• memory cells connected to said bit lines, said memory cells being arranged to define a plurality of cell sections each of which includes a selection transistor connected to a corresponding bit line and a series array of memory cell transistors connected at a first node thereof to said selection transistor and connected at a second node thereof to said substrate, each of said memory cell transistors having a charge storage layer and a control gate;
• parallel word lines provided above said substrate and connected to associated control gates of said memory cell transistors;
• and
• voltage applying means for reading out a data stored in a selected memory cell transistor in a certain cell section in a data read mode of said memory device, by rendering a selection transistor of said certain cell section conductive thereby to connect said certain cell section to a corresponding bit line associated therewith, applying a Low or "L" level voltage to a selected word line coupled to said selected memory cell transistor, and applying a pulsed voltage signal having a High or "H" level to non-selected word lines coupled to the remaining memory cell transistors in said certain cell section;
• wherein said voltage applying means comprises:
• first circuit means for generating, as said pulsed voltage signal having the "H" level, a voltage signal having a limited pulse width shorter than a period of a read cycle of said memory device, and
• second circuit means for determining a length of said pulse width.

An electrically erasable programmable semiconductor memory device comprising:

• a semiconductive substrate;
• an array of rows and columns of memory cells subdivided into a plurality of cell groups each including a predetermined number of series-connected memory cells having first and second nodes, each of said memory cells essentially consisting of a metal insulator semiconductor filed effect transistor having a charge storage layer and a control gate;
• parallel bit lines coupled to said cell groups;
• parallel word lines transverse to said bit lines and coupled to control gates of those transistors of the rows of memory cells;
• data reading means connected to said word lines, for reading a data stored in a desired memory cell being presently selected from a certain cell group in a read cycle, by applying a selected word line coupled to said desired memory cell with a Low or "L" level voltage, by applying non-selected word lines coupled to the remaining non-selected memory cells in said certain cell group with a High or "H" level voltage which is greater in potential than a power supply voltage in such a manner that said "H" level voltage is applied to said non-selected word lines for a limited period less in length than the read cycle;
• and
• said data reading means including,
• booster means for receiving the power supply voltage and for generating a potentially increased or bootstrapped voltage which is greater in potential than the power supply voltage as said "H" level voltage, and
• timer means arranged on said substrate for determining a predetermined period, and for forcing the application of said "H" level voltage to terminate within the read cycle when an elapsed time from the beginning of the potential change of said non-selected word lines becomes equal to the predetermined period in the read cycle, whereby a total application time of said "H" level voltage is shorter than a period of the read cycle.