Memory having looped global data lines for propagation delay matching

A synchronous static random access memory, comprising:

• a plurality of memory cells arranged in rows and columns, each memory cell coupled to a word line and to a bit line pair;
• a row select circuit, coupled to the plurality of memory cells, for selecting the word line in response to a row address;
• a column decoder, coupled to the plurality of memory cells, for selecting the bit line pair in response to a column address;
• a sense amplifier, coupled to the column decoder, for sensing and amplifying a differential data signal corresponding to a data bit from a selected memory cell during a read cycle of the memory;
• and
• a read global data line pair, coupled to the sense amplifier, and extending along an edge of the plurality of memory cells from a first end of the plurality of memory cells to a second end of the plurality of memory cells, the read global data line pair substantially parallel to a row select line, and at the second end of the plurality of memory cells, the read global data line pair extending back in an opposite direction and substantially parallel to the row select line;
• wherein the read global data line pair is for adjusting an access time from different locations in the plurality of memory cells.