Simulator for conducting timing analysis of a circuit

The simulator for simulating an operation of an object circuit having interconnected electronic elements while detecting a timing error in respective operations of said electronic elements, wherein at least one of said electronic elements is a delay element, and said object circuit has a plurality of input terminals to which a given plurality of test pattern signals are applied, respectively, said simulator comprising:

• (a) memory means having storage areas which are assigned to said electronic elements, respectively;
• (b) means for providing a timing check definition file specifying contents of said timing errors for said electronic elements of said object circuit;
• (c) means for generating an electronic status equivalently representing a situation where said plurality of test pattern signals are applied to said plurality of input terminals of said object circuit, respectively to simulate an operation of said object circuit under said situation;
• (d) means coupled to said means (a) and (c) for being informed from said means (c) that a level transition is caused on one of outputs of said electronic elements and for writing in information an a storage area which is included in said storage areas and is assigned to an electronic element on whose output said level transition is caused, where said information includes a first component representing contents of said level transition and a second component identifying an input terminal of said object circuit to which a test pattern signal causing said level transition is applied;
• (e) means coupled to said means (b) and (c) for detecting a timing error on respective inputs and outputs of said electronic elements on the basis of said timing check definition file in a simulation executed by said means (c);
• (f) means coupled to said means (a) and (c) for referring to said information written in a storage area which is included in said storage areas and is assigned to an electronic element at which said timing error is detected, to identify a test pattern signal which is included in said plurality of test pattern signals and has relation to said timing error, and
• (g) means coupled to said means (f) for outputting an error message including a first data representing contents of said timing error and a second data identifying said test pattern signal having relation to said timing error.