Video signal processing apparatus having series connected timing control circuits

A video signal processing apparatus, comprising:

• (a) signal processing means for processing a video signal, said signal processing means including a plurality of series-connected signal processing circuits;
• (b) reference signal generation means for generating a reference signal;
• and
• (c) timing control means including a plurality of timing control circuits for respectively controlling the plurality of signal processing circuits in accordance with the reference signal;
• wherein at least one of the plurality of timing control circuits receives a timing signal conforming to the reference signal, and delays the passage of the timing signal therethrough by a time period corresponding to a delay time of the video signal processed by the corresponding signal processing circuit and outputs a delayed timing signal, and
• wherein another of the plurality of timing control circuits controls the corresponding signal processing circuit in accordance with the delayed timing signal, and
• wherein a corresponding change in the delayed timing signal occurs when the timing control circuit that outputs the delayed timing signal is altered or replaced so that the changed delayed timing signal corresponds to a change in the delay time of the video signal processed by the altered or replaced corresponding signal processing circuit.

A video signal memorizing apparatus, comprising:

• (a) signal processing means for processing a video signal;
• (b) a memory for storing the video signal output from said signal processing means;
• (c) synchronizing signal separation means for separating a synchronizing signal from the video signal which is supplied to said signal processing means;
• (d) timing control means for timing the operation of said signal processing means on the basis of the separated synchronizing signal, said timing control means delaying the passage of the synchronizing signal therethrough by a time period corresponding to a delay time of the video signal processed by said signal processing means and outputting a delayed synchronizing signal;
• and
• (e) write control means for timing writing of the video signal in said memory using the delayed synchronizing signal output from said timing control means, wherein a corresponding change in the delayed synchronizing signal occurs when said timing control means is altered or replaced so that the changed delayed synchronizing signal corresponds to a change in the delay time of the video signal processed by the altered or replaced signal processing means.

A video signal recording apparatus, comprising:

• (a) first signal processing means for processing a video signal;
• (b) second signal processing means for processing the video signal output from said first signal processing means;
• (c) recording means for recording the video signal output from said second signal processing means on a recording medium;
• (d) reference signal generation means for generating a reference signal for timing the operation of said recording means;
• (e) first timing control means for timing the operation of said first signal processing means on the basis of the reference signal, said first timing control means delaying the reference signal by a time period corresponding to a delay time of the video signal processed by said first signal processing means and outputting a delayed reference signal;
• and
• (f) second timing control means for timing the operation of said second signal processing means using the delayed reference signal output from said first timing control means, wherein a corresponding change in the delayed reference signal occurs when said first timing control means is altered or replaced so that the changed delayed reference signal corresponds to a change in the delay time of the video signal processed by the altered or replaced first signal processing means.

A video signal reproducing apparatus, comprising:

• (a) reproduction means for reproducing a video signal from a recording medium;
• (b) reference signal generation means for generating a reference signal for timing the operation of said reproduction means;
• (c) first signal processing means for processing the video signal output from said reproduction means;
• (d) second signal processing means for processing the video signal output from said first signal processing means;
• (e) first timing control means for timing the operation of said first signal processing means on the basis of the reference signal, said first timing control means delaying the reference signal by a time period corresponding to a delay time of the video signal processed by said first signal processing means and outputting a delayed reference signal;
• and
• (f) second timing control means for timing the operation of said second signal processing means using the delayed reference signal output from said first timing control means, wherein a corresponding change in the delayed reference signal occurs when said first timing control means is altered or replaced so that the changed delayed reference signal corresponds to a change in the delay time of the video signal processed by the altered or replaced first signal processing means.

A video signal reading apparatus, comprising:

• (a) a memory for storing a video signal;
• (b) signal processing means for processing the video signal read out from said memory;
• (c) reference signal generation means including an oscillator for generating a predetermined clock signal;
• (d) read-out control means for timing read-out of the video signal from said memory on the basis of the reference signal, said read-out control means delaying the reference signal by a time interval required to read out the video signal from said memory and outputting a delayed reference signal;
• and
• (e) timing control means for timing the operation of said signal processing means using the delayed reference signal output from said read-out control means, wherein a corresponding change in the delayed reference signal occurs when said read-out control means is altered or replaced so that the changed delayed reference signal corresponds to a change in the delay time required to read out the video signal from the altered or replaced memory.

A signal process apparatus comprising:

• (a) forward signal processing means for processing a signal;
• (b) backward signal processing means for processing the signal output from said forward signal processing means;
• (c) reference signal generation means for generating a reference signal;
• (d) forward timing control means for timing an operation of said forward signal processing means on the basis of the generated reference signal, said forward timing control means delaying the reference signal by a time period corresponding to a delay time of the forward signal processing means, and for outputting a delayed reference signal;
• and
• (e) backward timing control means for timing the operation of said backward signal processing means on the basis of the delayed reference signal;
• wherein a corresponding change in the delayed reference signal occurs when said forward signal processing means is altered or replaced.

A signal processing comprising:

• (a) a plurality of signal processing means coupled in series;
• (b) reference signal generation means for generating a reference signal;
• and
• (c) a plurality of timing control means coupled in series, said plurality of timing control means including a forward timing control means for outputting a delayed reference signal which comprises said reference signal delayed by a predetermined period of time, said plurality of timing control means, other than said forward timing control means, respectively timing-controlling each of said plurality corresponding of signal processing means on the basis of said delayed reference signal;
• wherein said predetermined period of time is set in accordance with a processing time of the timing-controlled signal processing means, and wherein said delayed reference signal is supplied from said forward timing control means.