Multiple level parallel magnitude comparator

#1. Field of the Invention

#The present invention relates generally to integrated circuits, and more specifically to a multiple level magnitude comparator circuit.

#2. Description of the Prior Art

#The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

#FIG. 1 is a block diagram of a FIFO flag generation circuit according to the prior art;

#FIG. 2 is a schematic diagram of a serial magnitude comparator utilized in the prior art;

#A FIFO is a First In First Out memory typically used in prior art applications between machines which use data at different rates of speed: for instance, between a computer and a printer. The FIFO memory outputs its status through the use of a flag. Comparators are frequently used in FIFO memory circuits in conjunction with subtractors to generate FIFO flags. The flag outputs indicate that the FIFO is full, half full, and empty, for instance. In order to determine FIFO status, it is necessary to keep track of how many bits have been written in and how many bits have been read out of the FIFO. Also, it is necessary to know the relationship between the magnitude of two numbers and whether the magnitude of one number is equal to, less than, or greater than the magnitude of the second number. Comparing the magnitude of these numbers is accomplished through the use of a magnitude comparator circuit inside the FIFO.

#Referring to FIG. 1, a block diagram of a FIFO Flag generation circuit according to the prior art is shown. The FIFO Flag has a counter block 10, a subtractor block 12, a comparator block 14, and a deglitch block 16. The write clock 18, the read clock 20, the write reset clock 22, and the read reset clock 24 are input signals to both the counter block 10 and the deglitch block 16. The counter block 10 takes these input signals and generates a write count 26 and a read count 28 which are input to the subtractor block 12 which in turn outputs a difference signal 30. This difference signal 30 and a program value 32 are input to the comparator block 14 which compares them in order to generate an output compare signal 34. As is well known in the art, the program value 32 is set to different values depending on the type of flag signal 36, such as empty, half full, or full, to be generated. Finally, the compare signal 34 as well as the write clock 18, the read clock 20, the write reset clock 22, and the read reset clock 24 are input to the deglitch block 36 which generates a flag output signal 36.

#FIG. 2 shows a schematic diagram of a serial magnitude comparator 20 utilized in the prior art. The magnitude comparator 20 is responsible for determining the relationship between the magnitude of two numbers. The magnitude comparator 20 has a plurality of bit comparators 22, 24, 26, and 28 which determine the status of the relative magnitude of the two numbers being compared. The number of bit comparators needed is a function of the number of bits in the two numbers being compared. Each bit comparator compares a bit, at a certain bit position, from both numbers. For example, the magnitude status of the first bit to be compared, 40, is compared to that of the second bit 42 to determine if it is equal to, less than, or greater than the second bit 42. Every bit comparator has four inputs. The two bits to be compared, 40 and 42, are input to an exclusive OR gate 44, the output of which is input 36 of bit comparators 22, 24, 26 and 28; signal 36 is inverted to provide input 38. Input 38, which is simply the inverse of input 36, could easily be generated internal to the bit comparator, in which case it would not be an input signal. Other inputs to the bit comparators are the output of the previous bit comparator 30, and input 34, the first bit of the two bits being compared. Input 34 is different from program value 32 shown in FIG. 1. FIG. 2 shows two binary numbers being compared whereas FIG. 1 shows a binary number being compared with a fixed value represented by program value 32.