CMOS circuit providing 90 degree phase delay

In combination:

• means responsive to an input data signal for providing an output signal shifted in phase from the input data signal;
• means for providing an exclusive OR signal in response to the input data signal and the phase shift signal;
• phase-locked loop means comprising an oscillator having an output synchronized to said exclusive OR signal;
• and
• means for slaving said phase shift means to said phase-locked loop means to provide a phase shift of 90.degree. at the frequency of said oscillator output.

In combination:

• a phase shifter adapted to receive a non-return-to-zero input data signal and provide an output signal shifted in phase from the input data signal, said phase shifter comprising a plurality of delay circuits connected in a series;
• an exclusive OR responsive to the input data signal and the phase shifted signal from the phase shifter;
• a phase-locked loop comprising a ring oscillator for providing an output synchronized to an output of the exclusive OR, said ring oscillator comprising a plurality of delay circuits connected in a loop;
• and
• means for operating the delay circuits of said phase shifter in accordance with the delays of the delay circuits of said ring oscillator to provide a 90.degree. phase shift at the frequency of said output of said ring oscillator.

A clock and data recovery system for an incoming non-return-to-zero input data signal, comprising:

• a phase shifter comprising a plurality of differential inverters connected in series, said phase shifter being adapted to receive a non-return-to-zero input data signal at a first one of said differential inverters in said series and provide an output signal from a last differential inverter in said series wherein said output signal is shifted in phase from said data input signal;
• an exclusive OR responsive to the input data signal and the phase shifted signal from said phase shifter to provide a signal including a frequency component of an originating clock of said non-return-to-zero input data;
• a phase-locked loop comprising a current controlled oscillator and a phase detector responsive to said signal from said exclusive OR and an output from said current controlled oscillator, said current controlled oscillator comprising a ring oscillator of differential inverters and being responsive to said phase detector to cause said output of said current controlled oscillator to be driven into synchronism with said frequency component of said originating clock of said non-return-to-zero input data;
• said differential inverters of said phase shifter being replicas and being operated under the same operating and bias conditions as said differential inverters of said ring oscillator to produce a total delay equal to 90.degree. at the output frequency of said ring oscillator;
• said ring oscillator comprising an even number of differential inverters with the outputs of a single differential inverter being reversed to the inputs of another differential inverter in the ring of differential inverters to provide oscillation with said even number of differential inverters;
• said output from said current controlled oscillator to said phase detector being connected to the outputs of a first differential inverter;
• said current controlled oscillator having a quadrature output connected to the differential outputs of a differential inverter spaced half the total number of differential inverters in said ring from said first differential inverters;
• and
• a decision circuit having a data input fed by said non-return-to-zero input data signal and clock input fed by said quadrature output from said current controlled oscillator to provide clean logical outputs of l's and 0's.

A method of recovering a clock from a non-return-to-zero input data signal, comprising the steps of:

• shifting the phase of the non-return-to-zero input data signal to provide a phase shifted signal;
• exclusive ORing the input data signal and the phase shifted signal to provide an output signal having a frequency component of an originating clock of the non-return-to-zero input data signal;
• feeding the exclusive ORing output signal to a phase detector of a phase-locked loop further comprising a current controlled oscillator having an output fed to said phase detector to drive the output of said current controlled oscillator to the frequency of said originating clock of said non-return-to-zero input data signal;
• and
• controlling the delay of the phase shifting step in accordance with the phase-locked loop to provide a phase shift of 90.degree. at the output frequency of said current controlled oscillator.