Digital PLL circuit

A digital PLL circuit, comprising:

• a master clock oscillator for oscillating a master clock signal having a frequency equal to N times the frequency of an input clock signal, N being an integral number;
• a variable dividing ratio divider for dividing the master clock signal received from said master clock oscillator by a dividing ratio which is normally equal to N, the dividing ratio of said divider being temporarily variable to another integral number around N;
• a phase comparator for comparing the phases of a division output of said divider and the input clock signal with each other;
• a variable step number random walk filter interposed between said phase comparator and said divider and having a selectively settable integration time constant for providing an output to temporarily vary the dividing ratio of said divider;
• and
• an integration time constant setting circuit, coupled to said random walk filter, for varying the step number of said random walk filter in accordance with information of the last phase controlling direction and information of a phase controlling direction at present obtained from the output of said random walk filter to vary the integration time constant of said random walk filter.