Field programmable gate array device with antifuse overcurrent protection

A field programmable gate array having a plurality of logic modules, comprising:

• first and second sets of logic module interconnection lines;
• a pair of driver circuits, each of said driver circuits having an input and an output;
• the respective inputs being each commonly connected to receive a same output signal from a selected one of said logic modules;
• and
• first and second sets of antifuses interposed between respective ones of said outputs of said driver circuits and logic module interconnection lines of at least one of said first and second sets of said logic module interconnection lines, said antifuses providing means for selectively connecting said selected one of said logic modules to corresponding selected one of said logic module interconnection lines.

A method for operating a field programmable gate array having a plurality of logic modules and logic module interconnection lines, comprising:

• providing a pair of driver circuits, each of said driver circuits having an input and an output;
• commonly connecting the respective inputs of each driver circuit of said pair to receive a same output signal from a selected one of said logic modules;
• establishing the output from each of said driver circuits to provide a current magnitude less than a threshold current level that would damage an antifuse, but greater than a predetermined current magnitude;
• and
• arranging a pair of antifuses between respective outputs of said driver circuits and at least one of said logic module interconnection lines, for selectively connecting said selected one of said logic modules with said module interconnection lines in the formation of a user-defined logic circuit.

A field programmable gate array, comprising:

• a plurality of first tracks;
• a plurality of second tracks crossing said first tracks at intersections;
• an antifuse provided at each intersection of said first and second tracks;
• said antifuses being configured to be selectively blown to establish selected electrical connections at said intersections between selected ones of said first and second tracks;
• and said antifuses being characterized by critical threshold current ratings defining currents above which said antifuses may be damaged;
• a plurality of logic modules having output lines, respectively arranged to receive input logic signals from other elements on said gate array and to deliver output signals to said output lines;
• a plurality of driver circuits attached to each of said output lines;
• said driver circuits having inputs commonly connected to said output lines and outputs respectively connected to different ones of said second tracks so that multiple connections between a selected logic module output line and a selected first track can be established through said plurality of driver circuits by selectively blowing different ones of said antifuses connecting said different ones of said second tracks to said selected first track;
• whereby total current greater than said critical threshold current can be flowed from said selected logic module output line to said selected first track, without flowing current greater than said critical threshold current through any of said different ones of said antifuses.

A method of operating a field programmable gate array;

• said gate array comprising a plurality of first tracks;
• a plurality of second tracks crossing said first tracks at intersections;
• an antifuse provided at each intersection of said first and second tracks, said antifuses being characterized by a critical threshold current ratings defining currents above which said antifuses may be damaged;
• and a plurality of logic modules having output lines, respectively arranged to receive input logic signals from other elements on said gate array and to deliver output signals to said output lines;
• said method comprising the steps of:
• providing a plurality of driver circuits attached to each of said output lines;
• said driver circuits having inputs commonly connected to said output lines and outputs respectively connected to different ones of said second tracks;
• selectively blowing different ones of said antifuses connecting said different ones of said second tracks to a selected one of said first tracks to establish multiple connections between a selected logic module output line and said selected first track through said associated plurality of driver circuits;
• flowing a total current greater than said critical threshold current from said selected logic module output line to said selected first track, without flowing current greater than said critical threshold current through any of said different ones of said antifuses.