US 5,399,921 A · Dynamic complementary pass-transistor logic circuit

Abstract

A dynamic logic circuit style, which may be employed in fast logic circuits, is disclosed. The logic functionality is obtained using complementary pass transistor logic networks. Intermediate nodes and the complementary outputs are precharged to a high level during the precharge clock phase. During the evaluation clock phase, the inputs connected to gates of the pass transistors are constrained to either make a low-to-high transition or to maintain their initial low level; such signals are referred to as rising signals. The inputs connected to current electrodes of the pass transistors are constrained to either make a high-to-low transition or maintain their initial high level; such signals are referred to as falling signals. All signals are organized in pairs of true and complementary signals. In a falling signal pair, only one of the signals is allowed to make a high-to-low transition during an evaluation phase, while the other signal remains at the initial high level. In a rising signal pair, only one of the signals is allowed to make a low-to-high transition during an evaluation phase, while the other signal remains at the initial low level. This ensures that one of the true and complementary output nodes of the pass transistor networks makes a high-to-low transition, while the other node remains at a high level. The high-to-low transition is locally buffered by a clocked regenerative feedback circuit present on both output nodes. The signals on the output nodes form a pair of true and complementary signals which may be used as falling input signals for another circuit stage in the same circuit style. In the regenerative feedback circuits, the inverted output signals are produced and these signals form a pair of true and complementary rising signals which may be used as rising input signals for another circuit stage in the same circuit style.

In an integrated circuit, a dynamic logic circuit,

said dynamic:
logic circuit comprising a supply node, a ground node, a clock node, first and second precharged switch networks, a plurality of first input nodes, a plurality of second input nodes, first and second evaluation speed-up circuits first and second output nodes, third and fourth output nodes, and having a precharge and an evaluation clock phase,
said precharge clock phase being characterized by a predetermined logic level being asserted on said clock node, said evaluation clock phase being characterized by said predetermined logic level not being asserted on said clock node,
each of said first input nodes having a rising signal, said rising signal being characterized as a signal that is at a low logic level at the beginning of said evaluation clock phase, and that may make at most one level change during said evaluation clock phase,
each of said second input nodes having a falling signal, said falling signal being characterized as a signal that is at a high logic level at the beginning of said evaluation clock phase, and that may make at most one level change during said evaluation clock phase,
said first precharged switch network providing means for establishing a first electrically conductive path between said first output node and one of said second input nodes during said evaluation clock phase whereby said first electrically conductive path is determined by said first input nodes, and providing means for precharging said first output node to a high logic level during said precharge clock phase,
said second precharged switch network providing means for establishing a second electrically conductive path between said second output node and one of said second input nodes during said evaluation clock phase whereby said second electrically conductive path is determined by said first input nodes, and providing means for precharging said second output node to a high logic level during said precharge clock phase,
said first and second evaluation speed-up circuits each having first and second terminals and a clock input, said first terminal of said first evaluation speed-up circuit being connected to said first output node, said second terminal of said first evaluation speed-up circuit being connected to said fourth output node, said first terminal of said second evaluation speed-up circuit being connected to said first output node, said second terminal of said second evaluation speed-up circuit being connected to said third output node,
said first and second evaluation speed-up circuits each providing means for detecting a deviation larger than a predetermined threshold from said high logic level towards said low logic level on said first terminal during said evaluation clock phase, providing means to discharge said first terminal to said low logic level after detection of said deviation, providing means to charge said second terminal to said high logic level after detection of said deviation, and providing means to discharge said second terminal to said low logic level during said precharge clock phase.

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Dynamic complementary pass-transistor logic circuit

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Dynamic complementary pass-transistor logic circuit

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Abstract

Claims5