Large fan-in, dynamic, bicmos logic gate
AssigneeIntel Corporation
InventorsGregory F. Taylor, Lawrence T. Clark
Life of this patent
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Abstract
A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.
Claims24
A BiCMOS circuit which operates as a dynamic logic gate, said circuit having an input and an output, said circuit comprising:
- a first bipolar transistor having a base coupled to said input, an emitter coupled to said output, and a base-emitter junction;
- protection circuitry for raising a base voltage appearing at said base of said first bipolar transistor from a low base voltage to a higher base voltage when an emitter voltage appearing at said emitter of said first bipolar transistor switches from a low emitter voltage to a high emitter voltage thereby reducing or eliminating a reverse bias voltage appearing across said base-emitter junction;
- and
- a discharge transistor through which said base of said first bipolar transistor may be drained of charge in order to reset said BiCMOS circuit, said discharge transistor having a first and second end through which charge is drained, said first end of said discharge transistor being coupled to said base of said first bipolar transistor, said second end of said discharge transistor being coupled to a node, said node being separated from said emitter of said first bipolar transistor such that a voltage at said node is initially lower than a voltage at said emitter upon reset of said BiCMOS circuit.
A computer system comprising:
- a main memory means for storage of information;
- a processor means for manipulation of said information;
- a bus means for transferring said information between said main memory means and said processor means;
- said processor means including a bipolar transistor having a base coupled to an input, an emitter coupled to an output, and a base-emitter junction;
- said processor means additionally including a protection means for raising a base voltage appearing at said base of said bipolar transistor from a low base voltage to a higher base voltage when an emitter voltage appearing at said emitter of said bipolar transistor switches from a low emitter voltage to a high emitter voltage thereby reducing or eliminating a reverse bias voltage appearing across said base-emitter junction.
A method of improving the reliability of a BiCMOS circuit which operates as a dynamic logic gate, said circuit having an input and an output, said method comprising the step of providing protection circuitry to raise a low base voltage appearing at a base of a first bipolar transistor contained within said BiCMOS circuit to a higher base voltage when a low emitter voltage appearing at an emitter of said first bipolar transistor switches to a high emitter voltage, said input being coupled to said base and said output being coupled to said emitter, wherein said BiCMOS circuit comprises a discharge transistor through which said base of said first bipolar transistor may be drained of charge in order to reset said BiCMOS circuit, said discharge transistor having a first and second end through which charge is drained, said first end of said discharge transistor being coupled to said base of said first bipolar transistor, said second end of said discharge transistor being coupled to a node, said node being separated from said emitter of said first bipolar transistor such that a voltage at said node is initially lower than a voltage at said emitter upon reset of said BiCMOS circuit.
Dependencies are inferred from the claim text.