Drive circuit including two level-shift circuits
AssigneeNEC Corporation
InventorYukio Yahata
Life of this patent
Estimating the term…
Abstract
A drive circuit for an Electroluminesent display panel is disclosed in which a ground line is divided into two line, one of which is provided for a signal input stage and the other of which is provided for a signal output stage. The signal output stage includes two level-shift circuits, one operating by receiving a first power voltage between a first power line and the other ground line and the other operating by receiving a second power voltage between a second power line and the other ground line.
Claims7
A transistor circuit comprising a first power line transferring a first power voltage, a second power line transferring a second power voltage different from said first power voltage, a third power line transferring a reference voltage, a fourth power line transferring said reference voltage independently of said third power line, a first circuit connected between said first and third power lines and responding to an input data signal supplied thereto to produce true and complementary levels of said input data signal, and a second circuit connected between said second and third power lines and responding to said true and complementary levels derived from said first circuit to produce an output signal, said first circuit including first and second transistors having source-to-drain paths thereof connected in series between said first and third power lines and third and fourth transistors having source-to-drain paths thereof connected in series between said first and third power lines, said second transistor having a gate connected to a node of said third and fourth transistors and said fourth transistor having a gate connected to a node of said first and second transistors, and said second circuit including fifth and sixth transistors having source-to-drain paths thereof connected in series between said second and third power lines.
A transistor circuit comprising a first power line transferring a first power voltage, a second power line transferring a second power voltage different from said first power voltage, a third power line transferring a reference voltage, a fourth power line transferring said reference voltage independently of said third power line, a first circuit connected between said first and third power lines and responding to an input data signal supplied thereto to produce true and complementary levels of said input data signal, and a second circuit connected between said second and third power lines and responding to said true and complementary levels derived from said first circuit to produce an output signal, said first circuit including first and second transistors having source-to-drain paths thereof connected in series between said first and third power lines and third and fourth transistors having source-to-drain paths thereof connected in series between said first and third power lines, said second transistor having a gate connected to a node of said third and fourth transistors and said fourth transistor having a gate connected to a node of said first and second transistors, and said second circuit including fifth and sixth transistors having source-to-drain paths thereof connected in series between said second and third power lines and said second circuit including fifth and sixth transistors connected in series between said second and third power lines and seventh and eighth transistors connected in series between said second and third power lines, said fifth transistor having a gate connected to a node of said seventh and eighth transistors and said seventh transistor having a gate connected to a node of said fifth and sixth transistors.
A transistor circuit comprising:
- a first power line transferring a first power voltage;
- a second power line transferring a second power voltage different from said first power voltage;
- a third power line transferring a reference voltage;
- a fourth power line transferring said reference voltage independently of said third power line;
- a first circuit including first and second transistors having source-to-drain paths thereof connected in series between said first and fourth power lines for outputting a data signal;
- a second circuit including third and fourth transistors having source-to-drain paths thereof connected in series between said first and third power lines and responding to said data signal supplied thereto to produce an internal signal;
- and
- a third circuit including fifth and sixth transistors having source-to-drain paths thereof connected in series between said second and third power lines and generating in response to said internal signal an output signal.
Dependencies are inferred from the claim text.