Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error
AssigneeHitachi, Ltd.
InventorsShigeharu Murata, Takasi Oomori, Masami Usami, Masato Iwabuchi
Life of this patent
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Abstract
A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.
Claims20
A hold-type circuit which holds a result of a parity check outputted from a parity-checking circuit and which provides an output indicative of the parity check result, comprising:
- a latch circuit which holds the result of the parity check in response to clock signals;
- and
- a control circuit which is coupled to said latch circuit and which controls the holding of the result of the parity check in said latch circuit, wherein the result of the parity check held in said latch circuit remains unchanged if the output of said latch circuit indicates to said control circuit that the held result of the parity check represents an error in the parity check.
A semiconductor device comprising:
- a plurality of memory cells;
- means for checking data read out from said plurality of memory cells;
- and
- means for holding an output data of the checking means, said means for holding including:
- a data input terminal,
- a data output terminal,
- a latch circuit which receives via said data input terminal the output data from the checking means, which holds the output data received in response to clock signals, and which outputs the held output data to said data output terminal, and
- a control circuit which is adapted to maintain at a fixed level a logic state of the held output data outputted from said latch circuit, wherein said control circuit includes a feedback circuit that feeds the logic state of said data output terminal back to said data input terminal.
Dependencies are inferred from the claim text.