Semiconductor chip packaging structure including a ground plane
AssigneeInternational Business Machines Corporation
InventorsHarry R. Bickford, Paul W. Coteus, Linda C. Matthew
Life of this patent
Estimating the term…
Abstract
A semiconductor chip package wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that has a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.
Claims18
A semiconductor packaging structure comprising in combination:
- a semiconductor chip having a contact pad region in a surface thereof,
- said surface of said chip terminating in at least one edge,
- a multilayer wiring member, said multilayer wiring member having,
- at least one superimposed combination of layers of a conductor layer and a broad area metal layer,
- said broad area metal layer having at least a portion thereof being a metal mesh,
- each said conductor layer and said broad area metal layer combination being separated by a dielectric layer,
- said multilayer wiring member being positioned with a conductor layer of one said at least one combination of said superimposed said conductor layer and said broad area metal layer adjacent said chip surface,
- said multilayer wiring member having at least one external contact member portion,
- said at least one external contact member portion extending beyond said edge of said chip,
- at least one bond joining a conductor on said conductor layer with an adjacent pad in said contact pad region in said surface of said chip,
- at least one said bond being surrounded by a quantity of bond protecting encapsulation,
- said metal mesh portion of said at least one broad area metal layer including a surrounded area of mesh metal electrically separated from the remainder of said metal mesh area portion, and,
- a covering of encapsulating material extending over said at least one bond and said multilayer wiring member leaving exposed each said at least one external contact member portion of said multilayer wiring member.
A semiconductor packaging structure comprising in combination:
- a base of encapsulating material having at least one edge and a surface,
- a semiconductor chip having a contact pad region in a surface thereof,
- said semiconductor chip being embedded in said base with said contact pad region essentially flush with said surface of said base,
- a multilayer wiring member, said multilayer wiring member having superimposed layers of
- at least one conductor layer and
- a broad area metal layer said broad area metal layer having included therein a portion of said area of metal mesh,
- said broad area metal layer having further included therein a surrounded area of metal mesh electrically separated from said mesh portion,
- said multilayer wiring member being positioned with one said conductor layer adjacent said chip surface,
- said multilayer wiring member having at least one external contact member portion,
- said at least one external contact member portion extending beyond said edge of said base,
- at least one bond joining a conductor on said conductor layer with an adjacent pad in said contact pad region in said surface of said chip,
- at least one said bond being surrounded with bond protecting encapsulation, and,
- a covering of encapsulating material extending over said at least one bond and said multilayer wiring member leaving exposed each said at least one external contact member portion of said multilayer wiring member.
A multilayer wiring structure comprising in combination an area of superimposed layers of at least one layer of metal wiring conductors and at least one broad metal layer having at least a portion thereof a mesh of metal conductors and open areas, each said metal wiring conductor layer and said broad metal layer being separated by a layer of dielectric, and, in said mesh portion of said broad metal layer, there is a surrounded area of mesh metal electrically separated from the remainder of said mesh metal portion.
In a semiconductor chip wiring package wherein electrical interconnection between external wiring locations and connections to pads in an area of a surface of a chip are through conductors supported by dielectric, the improvement comprising:
- a multilayer wiring member,
- said multilayer wiring member having superimposed layers of wiring conductor metal and broad area metal separated by a layer of dielectric,
- said multilayer wiring member having an area opening corresponding to said area of said pads in said surface of said chip,
- said multilayer wiring member being positioned with said wiring conductor metal layer adjacent said chip and with said pad area of said chip surrounded by said opening,
- at least one bond providing electrical connection from at least one pad in said pad area in said surface of said chip to at least one wiring conductor in said wiring conductor metal layer, and,
- at least one external conductor portion of said superimposed layers each extending to an external wiring location.
Dependencies are inferred from the claim text.