Method for manufacturing improved lightly doped diffusion (LDD) semiconductor device
AssigneeSeiko Epson Corporation
InventorMatsuo Ichikawa
Life of this patent
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Abstract
A semiconductor device comprises at least one p-type and n-type LDD transistors in a pair and a standard (non-LDD) transistor in the same substrate. Appropriate p-wells and n-wells are formed in the substrate, gate electrodes deposited, p-type and n-type first diffusions made, a silicon nitride layer is deposited and removed to leave behind sidewalls on the gates, p-type and n-type second diffusions are made in the LDD transistors, the silicon nitride sidewalls are washed away with a solvent that attacks only the silicon nitride, a third diffusion is made in the standard (non-LDD) transistor(s), a phosphosilicate glass (PSG) layer is applied, contact holes are etched, and an aluminum metalization layer is applied and etched for the interconnect.
Claims14
A method for manufacturing complementary metal-oxide-semiconductor transistors in a semiconductor substrate, the transistors including a first transistor having a channel of a first conductivity type and a second transistor having a channel of a second conductivity type, the method comprising:
- forming first and second gates on the substrate for the first and second transistors, respectively;
- forming a thin insulating layer over the gates and the substrate;
- forming a lightly doped region of the first conductivity type that partially extends underneath each side of the first gate in the substrate;
- forming a lightly doped region of the second conductivity type that partially extends underneath each side of the second gate in the substrate;
- concurrently forming sidewalls on the two sides of the first and second gates;
- forming a heavily doped region of the first conductivity type on each side of the first gate in the substrate using the first gate and the sidewalls on the first gate as a mask;
- forming a heavily doped region of the second conductivity type on each side of the second gate in the substrate using the second gate and the sidewalls on the second gate as a mask;
- and
- concurrently removing the sidewalls on the two sides of the first and second gates so that the first and second transistors are formed as LDD type transistors.
A method for manufacturing complementary metal-oxide-semiconductor transistors in a semiconductor substrate, the transistors including a first transistor having a channel of a first conductivity type, and second and third transistors each having a channel of a second conductivity type, the method comprising:
- forming first, second and third gates on the substrate for the first, second and third transistors, respectively;
- forming a thin insulating layer over the gates and the substrate;
- forming a lightly doped region of the first conductivity type that partially extends underneath each side of the first gate in the substrate;
- forming a lightly doped region of the second conductivity type that partially extends underneath each side of the second and third gates in the substrate;
- concurrently forming sidewalls on the two sides of the first, second and third gates;
- forming a heavily doped region of the first conductivity type on each side of the first gate in the substrate using the first gate and the sidewalls on the first gate as a mask;
- forming a heavily doped region of the second conductivity type on each side of the second gate in the substrate using the second gate and the sidewalls on the second gate as a mask;
- concurrently removing the sidewalls on the two sides of the first, second and third gates so that the first and second transistors are formed as LDD type transistors;
- and
- forming a heavily doped region of the second conductivity type on each side of the third gate in the substrate so that the third transistor is formed as a non-LDD type transistor.
Dependencies are inferred from the claim text.