US 5,398,328 A · System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders

Abstract

A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

Claims9

Dependent claims

A method for converting a program designed to be executed on a computer system employing a first memory order to a program which is executable on a computer system employing a second memory order, the second memory order being the reverse of the first memory order, the method comprising the steps of:

(a) finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;
(b) combining the two least significant bits of each byte address with binary three using an exclusive-OR logic function, thereby generating two complementary bits for each byte address;
and
(c) replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.

1 more element

Dependencies are inferred from the claim text.

System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders

Life of this patent

System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders

Life of this patent

Abstract

Claims9