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US 5,398,327 AGranted
Central processing unit including two-valued/n-valued conversion unit
AssigneeSharp Kabushiki Kaisha
InventorYukihiro Yoshida
Life of this patent
Estimating the term…
Abstract
A central processing unit comprises a bidirectional circuit for converting a binary data and a binary address supplied from a binary logic circuit in the CPU into n-valued (n is an integer of 3 or larger) data and an n-valued address, respectively, and transmitting converted signals to the outside, and for converting n-valued data and an n-valued address supplied from the outside into binary data and a binary address, respectively, and transmitting converted signals to the binary logic circuit.
Claims13
An N-bit central processing unit comprising:
- a binary logic circuit;
- bus means connected to said binary logic circuit and provided with N signal lines for transmitting a piece or binary logic information from and to said binary logic circuit;
- connect means provided with at least a set of M signal lines for receiving and transmitting a piece of n-valued logic information from and to outside said central processing unit, wherein M=N.multidot.log(2)/log(n) and n is an integer of 3 or larger;
- first means for converting in parallel a binary data of N bits, a binary address of N bits and binary control data of N bits supplied via said bus means from said binary logic circuit into an n-valued data of M digits, an n-valued address of M digits and an n-valued control data of M digits, and transmitting the converted data, address and control data to said connect means to deliver said converting data toward outside the central processing unit;
- and
- second means for converting in parallel an n-valued address of M digits, an n-valued address of M digits and an n-valued control data of M digits supplied from said connect means into a binary data of N bits, a binary address of N bits and binary control data of N bits, and transmitting said converted data, address and control data to said binary logic circuit via said bus means.
3 more elements
A computer comprising:
- a. a central processing unit including
- (a) a binary logic circuit;
- (b) bus means connected to said binary logic circuit and provided with three sets of N signal lines for transmitting a binary logic data, a binary address and a binary control data from and to said binary logic circuit;
- (c) connect means provided with three sets of M signal lines for receiving and transmitting an n-valued logic data, an n-valued address and n-valued control data from and to outside said central processing unit, wherein M=N.multidot.log(2)/log(n) and n is an integer of 3 or larger;
- (d) first means for converting in parallel a binary data of N bits, a binary address of N bits and a binary control data of N bits supplied via said bus means from said binary logic circuit into an n-valued data of M digits, an n-valued address of M digits and an n-valued control data of M digits, and transmitting the converted data, address and control data to said connect means to deliver them toward outside the central processing unit;
- and
- (e) second means for converting in parallel an n-valued data of M digits, an n-valued address or M digits and an n-valued control data of M digits supplied from said connect means into a binary data of N bits, a binary address of N bits and a binary control data of N bits, and transmitting the converted data, address and control data to said binary logic circuit via said bus means;
- b. a data bus connected to said central processing unit through said connect means and provided with M signal lines for transmitting an n-valued data;
- c. an address bus connected to said central processing unit through said connect means and provided with M signal lines for transmitting an n-valued address;
- d. a control data bus connected to said central processing unit through said connect means and provided with M signal lines for transmitting an n-valued control data;
- e. a storage unit connected said data bus, address bus and control bus and provided with an n-valued/binary address conversion circuit for converting an n-valued address applied thereto through said address bus from said central processing unit into a binary address;
- and
- f. a peripheral unit connected said data bus, address bus and control bus and provided with an n-valued/binary address conversion circuit for converting an n-valued address applied thereto through said address bus from said central processing unit into a binary address.
10 more elements
An input/output device comprising:
- bus means provided with N signal lines for transmitting a piece of binary logic information;
- connect means provided with M signal lines for receiving and transmitting a piece of n-valued logic information from and to outside said device, wherein M=N.multidot.log (2)/log(n) and n is an integer of 3 or larger;
- first means for converting in parallel a piece of binary logic information of N bits supplied via said bus means into a piece of n-valued logic information of M digits, and transmitting the converted information to said connect means to deliver it toward outside said input/output device;
- and
- second means for converting in parallel a piece of n-valued logic information of M digits supplied from said connect means into a piece of binary logic information of N bits, and transmitting the converted information to said bus means;
- wherein said first and second converting means are composed of a bidirectional binary/n-valued conversion circuit including logical circuits.
3 more elements
Dependencies are inferred from the claim text.