US 5,398,326 AGranted

Method for data communication

AssigneeDallas Semiconductor Corporation

InventorRobert D. Lee

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Abstract

A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from a host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, the host system, after the falling edge, attempts to pull the data line high again, and then tests the potential of the data line to ascertain the value of the bit read.

A method for data communication by serial block transfers of data on a data line between a first system and at least one second system, said serial block transfers of data having at least one data bit and said data line having at least one voltage state, comprising the steps of:

(a) defining a current operating mode to be either a write mode or a read mode, so that said at least one data bit of said serial block transfers of data is transferred from said first system to said at least one second system when said current operating mode is said write mode and said at least one data bit of said serial block transfers of data is transferred from said at least one second system to said first system when said current operating mode is said read mode;
(b) driving said data line toward a first voltage level by said first system and thereafter driving said data line to make a transition of said data line toward a second voltage;
(c) detecting said transition of said data line toward said second voltage level by said at least one second system;
(d) and when said current operating mode is said read mode,
(d1) driving said data line toward said second voltage level by said at least one second system and holding said data line at said second voltage level for a first time duration, said first time duration having a first length, said first length dependent upon said at least one data bit of said serial block transfers of data and releasing said data line after said first time duration, and
(d2) testing the at least one voltage state of said data line by said first system within a time window, said time window terminates before a minimum possible duration of said first time duration;
(e) and when said current operating mode is said write mode,
(e1) driving said data line toward a data voltage level dependent upon said at least one data bit of said serial block transfers of data said data voltage level approximately equal to said first voltage level or said second voltage level;
(e2) waiting for a second time duration, said second time duration having a second length, said second length dependent upon said at least one data bit of said serial block transfers of data and then testing the at least one voltage state of said data line to ascertain the at least one data bit of said serial block transfers of data written;
and
(e3) in said first system, holding said data line to said data voltage level over said time window which begins before an earliest possible expiration, for said at least one second system of said second time duration, and which ends after a latest possible expiration, of said second time duration.

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Facts

Application

08/019,932Filed 19 Feb 1993 · division

Priority

15 May 1989

Granted

14 Mar 1995

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

G11C 8/20
Arrangements for selecting an address in a digital store: address safety or protection circuits, i.e. arrangements for preventing unauthorized or…
G06F 3/0383
Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry: signal control means within the pointing device
G06F 3/04897
Using dedicated keyboard keys or combinations thereof: special input arrangements or commands for improving display capability
G06K 7/0008
Methods or arrangements for sensing record carriers, e.g. for reading patterns: general problems related to the reading of electronic memory…

Abstract

Claims25