US 5,398,325 AGranted

Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems

AssigneeSun Microsystems, Inc.

InventorsJung-Herng Chang, Curt Berg, Jorge Cruz-Rios

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Abstract

Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus. A virtual bus interface (VBI) receives entries made in the input buffer, whereafter the input buffer is relieved to accept other commands. A cache invalidation queue (CIQ) register stores addresses of cache subblocks to which incoming invalidate operations have been directed. The address of the destination device is also written to the output buffer. If the address of the destination device stored in the output buffer matches the address in the CIQ register, the CC will issue a read-invalidate command, wherein the invalidated block of cache is again filled with data corresponding to the prior-accessing processor, thus invalidating the intervening overwrite issued by the later accessing CPU. Response time to snooping requests is thereby bounded, and data consistency between cache and processor are thereby maintained.

Claims12

Dependent claims

In a computer system comprising processor modules including a central processing unit (CPU), computer devices, and a main memory, a single copy cache tag cache memory structure comprising:

a cache intercoupled to said CPU by a first bus, said cache comprising a plurality of blocks further comprising a plurality of subblocks, and,
a cache controller coupled to said first bus and said cache, said cache controller further comprising:
a cache directory coupled to said cache and said CPU by said first bus, said main memory coupled to said cache controller by a second bus, said computer devices coupled to said cache controller by said second bus;
a plurality of tag entries comprising address tags, said plurality of tag entries further comprising a plurality of status bit fields corresponding to said subblocks, said tag entries pointed to by a cache directory index comprising a cache directory index field of a physical address;
first bus interface and control means coupled to said first bus for controlling data transfer on said first bus;
second bus interface and control means coupled to said second bus for controlling data transfer on said second bus;
a first bus command module for routing a plurality of second bus access requests issued from said CPU directed to said second bus, said first bus command module coupled to said first bus interface and control means;
a second bus command module for routing a plurality of first bus access requests issued from said computer devices coupled to the second bus and from said main memory directed to said first bus, said second bus command module coupled to said first bus interface and control means;
first buffer means coupled to said first and second bus command modules and to said second bus interface and control means for buffering commands directed by said CC to said second bus;
and,
second buffer means coupled to said second bus command module and to said second bus interface and control means for buffering commands directed by said second bus to said CPUs operating on said first bus.

8 more elements

In a computer system comprising processor modules including a central processing unit (CPU), computer devices, and a main memory, a single copy cache tag cache memory structure comprising:

a cache intercoupled to said CPU by a first bus, said cache comprising a plurality of blocks further comprising a plurality of subblocks, and,
a cache controller coupled to said first bus and said cache, said cache controller further comprising:
a cache directory coupled to said cache and said CPU by said first bus, said main memory coupled to said cache controller by a second bus, said computer devices coupled to said cache controller by said second bus;
a plurality of tag entries comprising address tags, said plurality of tag entries further comprising a plurality of status bit fields corresponding to said subblocks, said tag entries pointed to by a cache directory index comprising a cache directory index field of a physical address;
first bus interface and control means coupled to said first bus for controlling data transfer on said first bus;
second bus interface and control means coupled to said second bus for controlling data transfer on said second bus;
a first bus command module for routing a plurality of second bus access requests issued from said CPU directed to said second bus, said first bus command module coupled to said first bus interface and control means;
wherein said first bus command module further comprises:
first bus interface means coupled to said first bus command module for communicating with said first bus;
first bus arbitration means coupled to said first bus for controlling access to said first bus;
virtual bus interface means coupled to said first bus and said first and second bus command modules for reducing latency of first commands directed to said CPU;
wherein said virtual bus interface means comprises a fourth buffer coupled to said second bus command module;
said fourth buffer receiving a plurality of said first commands directed to said CPU by said computer devices operating on said second bus;
said fourth buffer, after receiving said first commands directed to said CPU, buffering said first commands until control of said first bus is granted to said first bus command module by said first bus arbitration means, said fourth buffer thereafter redirecting said first commands to said CPU;
a second bus command module for routing a plurality of first bus access requests issued from said computer devices coupled to the second bus and from said main memory directed to said first bus, said second bus command module coupled to said first bus interface and control means;
first buffer means coupled to said first and second bus command modules and to said second bus interface and control means for buffering commands directed by said CC to said second bus;
wherein said first buffer means further comprises:
a first buffer coupled to said first bus command module and receiving request commands directed from said first bus to said computer devices operating on said second bus, including said main memory;
a second buffer coupled to said second bus command module and receiving reply commands directed by said CC to said computer devices operating on said second bus, including said main memory;
wherein said first buffer means further comprises a local data bus coupled to receive said request and reply commands buffered by said first and second buffers, said local data bus further coupled to said second bus command module and transmitting said reply commands to said computer devices operating on said second bus, including said main memory;
second buffer means coupled to said second bus command module and to said second bus interface and control means for buffering commands directed by said second bus to said CPU's operating on said first bus;
wherein said second buffer means further comprises:
a third buffer coupled to said second bus command module for receiving said request commands directed to said CPUs and said CC by devices operating on said second bus, including said main memory;
wherein cache invalidating queue means for determining when a prior-occurring cache invalidating instruction has invalidated data in a particular subblock;
said cache invalidation queue means coupled to said second bus interface and control means and storing the addresses of subblocks to which are directed a plurality of shared-access operations;
said cache invalidation queue means further coupled to said second buffer means;
said second buffer means storing, in said second buffer, addresses of a plurality of destination devices operating on said second bus associated with said shared-access operations;
a match logic unit for comparing entries in said cache invalidation queue means and said second buffer means, said match logic unit coupled to said cache invalidation queue means and said second buffer means;
when said addresses of said destination devices matches said the address of said particular subblock, said cache invalidation queue means signaling said cache controller to fill said particular subblock with data that existed prior to said cache invalidating instruction, before completing said shared-access operation to said destination device;
receiving in said fourth buffer a plurality of first commands directed to said CPU by said devices operating on said second bus;
and,
after receiving said first commands directed to said CPU, buffering said first commands in said fourth buffer until control of said first bus is granted to said first bus command module by said first bus arbitration means, said fourth buffer thereafter redirecting said first commands to said CPU.

29 more elements

In a computer system comprising processor modules including a central processing unit (CPU), computer devices, and a main memory, a single copy cache tag cache memory structure comprising:

a cache intercoupled to said CPU by a first bus, said cache comprising a plurality of blocks further comprising a plurality of subblocks, and,
a cache controller coupled to said first bus and said cache, said cache controller further comprising:
a cache directory coupled to said cache and said CPU by said first bus, said main memory coupled to said cache controller by a second bus, said computer devices coupled to said cache controller by said second bus;
a plurality of tag entries comprising address tags, said plurality of tag entries further comprising a plurality of status bit fields corresponding to said subblocks, said tag entries pointed to by a cache directory index comprising a cache directory index field of a physical address;
first bus interface and control means coupled to said first bus for controlling data transfer on said first bus;
second bus interface and control means coupled to said second bus for controlling data transfer on said second bus;
a first bus command module for routing a plurality of second bus access requests issued from said CPU directed to said second bus, said first bus command module coupled to said first bus interface and control means;
wherein said first bus command module further comprises:
first bus interface means coupled to said first bus command module for communicating with said first bus;
first bus arbitration means coupled to said first bus for controlling access to said first bus;
virtual bus interface means coupled to said first bus and said first and second bus command modules for reducing latency of first commands directed to said CPU;
wherein said virtual bus interface means comprises a fourth buffer coupled to said second bus command module;
said fourth buffer receiving a plurality of said first commands directed to said CPU by said computer devices operating on said second bus;
said fourth buffer, after receiving said first commands directed to said CPU, buffering said first commands until control of said first bus is granted to said first bus command module by said first bus arbitration means, said fourth buffer thereafter redirecting said first commands to said CPU;
a second bus command module for routing a plurality of first bus access requests issued from said computer devices coupled to the second bus and from said main memory directed to said first bus, said second bus command module coupled to said first bus interface and control means;
first buffer means coupled to said first and second bus command modules and to said second bus interface and control means for buffering commands directed by said CC to said second bus;
wherein said first buffer means further comprises:
a first buffer coupled to said first bus command module and receiving request commands directed from said first bus to said computer devices operating on said second bus, including said main memory;
a second buffer coupled to said second bus command module and receiving reply commands directed by said CC to said computer devices operating on said second bus, including said main memory;
wherein said first buffer means further comprises a local data bus coupled to receive said request and reply commands buffered by said first and second buffers, said local data bus further coupled to said second bus command module and transmitting said reply commands to said computer devices operating on said second bus, including said main memory;
second buffer means coupled to said second bus command module and to said second bus interface and control means for buffering commands directed by said second bus to said CPUs operating on said first bus;
wherein said second buffer means further comprises:
a third buffer coupled to said second bus command module for receiving said request commands directed to said CPUs and said CC by devices operating on said second bus, including said main memory;
wherein cache invalidating queue means for determining when a prior-occurring cache invalidating instruction has invalidated data in a particular subblock;
said cache invalidation queue means coupled to said second bus interface and control means and storing the addresses of subblocks to which are directed a plurality of shared-access operations;
said cache invalidation queue means further coupled to said second buffer means;
said second buffer means storing, in said second buffer, addresses of a plurality of destination devices operating on said second bus associated with said shared-access operations;
a match logic unit for comparing entries in said cache invalidation queue means and said second buffer means, said match logic unit coupled to said cache invalidation queue means and said second buffer means;
when said addresses of said destination devices matches said the address of said particular subblock, said cache invalidation queue means signaling said cache controller to fill said particular subblock with data that existed prior to said cache invalidating instruction, before completing said shared-access operation to said destination device;
receiving in said fourth buffer a plurality of first commands directed to said CPU by said devices operating on said second bus;
after receiving said first commands directed to said CPU, buffering said first commands in said fourth buffer until control of said first bus is granted to said first bus command module by said first bus arbitration means, said fourth buffer thereafter redirecting said first commands to said CPU;
a method of determining when a prior-occurring cache invalidating instruction has overwritten data in a particular subblock;
comprising the steps of;
storing in said cache invalidation queue means the addresses of subblocks to which are directed a plurality of shared-access operations;
storing, in said second buffer, addresses of a plurality of destination devices operating on said second bus associated with said shared-access operations;
and,
comparing entries in said cache invalidation queue means and said second buffer means with said match logic unit coupled to said cache invalidation queue means and said second buffer means;
when said addresses of said destination devices matches said address of said particular subblock, signaling said cache controller to fill said particular subblock with data that existed prior to said cache invalidating instruction, before completing said shared-access operating to said destination device.

35 more elements

Dependencies are inferred from the claim text.