An information processing system for use in combination with a duplex storage having first and a second storages, the information processing system comprising:
- a bus;
- a main memory, including a data area, connected to said bus;
- a central processor including a control signal producer connected to said bus for producing a duplex write control signal indicative of data transfer from said data area to said first and said second storages and for delivering said duplex write control signal to said bus;
- and
- a duplex storage controller including:
- an input-output controller connected to said bus for producing a first and a second write control signal in response to said duplex write control signal received from said bus, said first write control signal being indicative of data transfer from said data area to said first storage, and said second write control signal being indicative of data transfer from said data area to said second storage;
- a first DMA controller including a first local memory connected to said input-output controller for memorizing said first write control signal as a first memorized write control signal and a first DMA control unit connected to said first storage, said bus and said first local memory for producing a first data transfer request in response to said first memorized write control signal;
- a second DMA controller including a second local memory connected to said input-output controller for memorizing said second write control signal as a second memorized write control signal and a second DMA control unit connected to said second storage, said bus and said second local memory for producing a second data transfer request in response to said second memorized write control signal;
- a request controller connected to said first and said second DMA control units for selecting a particular one of said first and said second data transfer requests as a first selected transfer request to produce said first selected transfer request and a particular unit signal representative of a particular one of a said first and said second DMA control units that produces said first selected transfer request;
- a data buffer memory connected to said bus;
- and
- a data buffer controller connected to said first and said second DMA control units for controlling said particular one of said first and said second DMA control units in response to said first selected transfer request and said particular unit signal to read data from said data area on said bus and to write said data in a particular one of said first and said second storages connected to said particular one of said first and said second DMA control units, said data buffer controller connected to said data buffer memory for making said data buffer memory memorize said data produced on said bus;
- said particular one of said first and said second DMA control units producing an end signal representative of an end of the data transfer from said data area to said particular one of said first and said second storages;
- said request controller selecting, in response to said end signal, a different one of said first and said second data transfer requests as a second selected transfer request to produce said second selected transfer request and a different unit signal representative of a different one of said first and said second DMA control units that produces said second selected transfer request;
- said data buffer memory connected to said first and said second DMA control units;
- said data buffer controller reading said data from said data buffer memory in response to said second selected transfer request and said different unit signal and controlling said different one of said first and said second DMA control units in response to said second selected transfer request and said different unit signal to write said data in a different one of said first and said second storages connected to said different one of said first and said second DMA control units.