High speed, low noise output buffer with non-identical pairs of output transistors

A semiconductor integrated circuit for charging and discharging an external load comprising:

• a plurality of output transistors coupled in parallel with each other, one end of each transistor being coupled to a power supply terminal or to a ground terminal, and other end of each transistor being coupled to the external load through an output terminal,
• wherein said plurality of output transistors form an output buffer circuit coupled to an input terminal through driving circuits which control on/off switching of said plurality of output transistors,
• wherein at least one of said plurality of output transistors has characteristics different from characteristics of the other output transistors of said plurality of output transistors wherein starting time of said at least one of said output transistors will be different from starting times of said other output transistors during both charging and discharging operations of said external load, and
• wherein at least one of said driving circuits has a driving capacity different from driving capacities of the other driving circuits wherein starting time of an output transistor coupled to said at least one of said driving circuits will be different from starting times of the other output transistors during both charging and discharging operations of said external load.

A semiconductor integrated circuit for charging and discharging an external load comprising:

• a first plurality of output transistors coupled in parallel to one another, each having one end coupled to a power supply terminal through a first common joining node and another end coupled to the external load through a second common joining node;
• and
• a second plurality of output transistors coupled in parallel to one another and disposed between said second common joining node and a ground terminal,
• wherein each of said first plurality of output transistors includes a control terminal coupled with a control terminal of one of said second plurality of output transistors through a third common joining node, said each control terminal being further connected to one end of respective driving circuits through the third common joining node, and further wherein other ends of said plurality of driving circuits are coupled to an internal circuit through a fourth common joining node, and
• wherein at least one of said first plurality of output transistors has characteristics different from characteristics of the other transistors of said first plurality of output transistors so that starting times of said at least one of said first plurality of output transistors will be different from starting times of the other transistors of said first plurality of output transistors during both charging and discharging operations of said external load, and wherein at least one of said second plurality of output transistors has characteristics different from characteristics of the other transistors of said second plurality of output transistors wherein starting times of said at least one of said second plurality of output transistors will be different from starting times of the other transistors of said second plurality of output transistors during both charging and discharging operations of said external load.

A semiconductor integrated circuit for charging and discharging an external load comprising:

• at least two bipolar transistors coupled in parallel, collectors of said bipolar transistors being coupled to a power supply terminal through a common joining node, emitters of the bipolar transistors being coupled to the external load through an output terminal through another common joining node and a diode, and each base part of the bipolar transistors being coupled to a driving circuit, respectively;
• and
• at least two MOS transistors coupled in parallel, drains of said MOS transistors being coupled to said output terminal through a common joining node, sources of the MOS transistors being connected to a ground terminal through another common joining node, and gates of the MOS transistor being coupled to driving circuits, said driving circuits also being coupled to an input terminal,
• wherein at least one of said bipolar transistors has a smaller size than the other bipolar transistors, and at least one of said MOS transistors has a smaller size than the other MOS transistors wherein the starting times of said at least one of said bipolar transistors will be different from starting times of the other bipolar transistors during both charging and discharging operations of said external load, and so that starting times of said at least one of said MOS transistors will be different from starting times of the other MOS transistors during both charging and discharging operations of said external load.

A semiconductor integrated circuit for charging and discharging an external load coupled to an output node of the semiconductor integrated circuit comprising:

• a first pair of output transistors coupled in parallel with one another between a first power supply terminal and the output node;
• a second pair of output transistors coupled in parallel with one another between a second power supply terminal and said output node;
• a first driving means coupled between an input terminal and respective control terminals of said first pair of output transistors;
• a second driving means coupled between said input terminal and respective control terminals of said second pair of output transistors;
• and
• a two-level preset means coupled to said output node, including means for increasing a voltage of the output node to a predetermined first level prior to an input signal being provided to said input terminals when the voltage level of the output node is at a predetermined low level, and further including means for decreasing the voltage of the output node to a predetermined second level prior to an input signal being provided to said input terminal when the voltage level of the output node is at a predetermined high level,
• wherein said first pair of output transistors have characteristics different from one another wherein starting times of said first pair of transistors will be different from one another during both charging and discharging operations of said external load, and wherein said second pair of transistors have characteristics different from one another wherein starting times of said second pair of transistors will be different from one another during both charging and discharging operations of said external load.