US 5,398,316 AGranted

Devices, systems and methods for accessing data using a pixel preferred data organization

AssigneeTexas Instruments Incorporated

InventorsKarl M. Guttag, Richard D. Simpson, Robert J. Gove

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Abstract

A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs. Second memory has a second storage location storing the first portion of the second word accessible by the first inputs and the third set of bits received at the second inputs. Processing system includes a processor operating in a first mode to access a selected one of the first and second words and in a second mode to access a selected one of the first and second portions of both the first and second words.

Claims39

Dependent claims

A processing system operating on data words each having at least first and second portions comprising:

a first memory bank comprising:
first memory, first and second sets of address inputs associated with said first memory, including a first storage location for storing said first portion of a first data word and accessible by a first set of address bits being received at said first set of address inputs and a second set of address bits being received at said second set of address inputs, and a second storage location for storing said second portion of a second data word and accessible by said first set of address bits being received at said first set of address inputs and a third set of address bits being received at said second set of address inputs;
and
second memory, first and second sets of address inputs associated with said second memory, including a first storage location for storing said second portion of said first data word and accessible by said first set of address bits being received at said first set of address inputs and said second set of address bits being received at said second set of address inputs, and a second storage location for storing said first portion of said second data word, and accessible by said first set of address bits being received at said first set of address inputs and said third set of address bits being received at said second set of address inputs;
and
control circuitry:
accessing in a first mode a selected one of said first and second data words by providing said first set of address bits to said first set of address inputs associated with each of said first and second memories and a corresponding one of said second and third sets of bits to said second set of address inputs associated with each of said first and second memories;
and
accessing in a second mode a selected one of said first and second portions of both said first and second data words by providing said first set of address bits to said first set of address inputs associated with each of said first and second memories, providing a selected one of said second and third sets of bits to said second set of address inputs associated with said first memory and providing an other one of said second and third sets of bits to said second set of address inputs associated with said second memory.

6 more elements

A processing system operating on pixels having red, green, blue and alpha gun portions comprising:

a first memory bank comprising:
a first memory including a first storage location for storing said red gun portion of a first pixel and accessible by a set of primary address bits and a first set of least significant address bits, a second storage location for storing said green gun portion of a second pixel and accessible by said primary address bits and a second set of least significant address bits, a third storage location for storing said blue gun portion of a third pixel and accessible by said primary address bits and a third set of least significant address bits, and a fourth storage location for storing said alpha gun portion of a fourth pixel and accessible by said primary address bits and a fourth set of least significant bits;
a second memory including a first storage location for storing said alpha gun portion of said first pixel and accessible by said primary address bits and said first set of least significant address bits, a second storage location for storing said red gun portion of said second pixel and accessible by said primary address bits and said second set of least significant address bits, a third storage location for storing said green gun portion of said third pixel and accessible by said primary address bits and said third set of least significant address bits, and a fourth storage location for storing said blue gun portion of said fourth pixel and accessible by said primary address bits and a fourth set of least significant address bits;
a third memory including a first storage location for storing said blue gun portion of said first pixel and accessible by said primary address bits and said first set of least significant address bits, a second storage location for storing said alpha gun portion of said second pixel and accessible by said primary address bits and said second set of least significant address bits, a third storage location for storing said red gun portion of said third pixel and accessible by said primary address bits and said third set of least significant bits, and a fourth storage location for storing said green gun portion of said fourth pixel and accessible by said primary address bits and a fourth set of least significant address bits;
a fourth memory including a first storage location for storing said green gun portion of said first pixel and accessible by said primary address bits and said first set of least significant address bits, a second storage location for storing said blue gun portion of said second pixel and accessible by said primary address bits and said second set of least significant address bits, a third storage location for storing said alpha gun portion of said third pixel and accessible by said primary address bits and said third set of least significant bits, and a fourth storage location for storing said red gun portion of said fourth pixel and accessible by said primary address bits and a fourth set of least significant bits;
and
a processor:
accessing in a first mode a selected one of said first, second, third and fourth pixels by presenting each of said first, second, third and fourth memories with said primary address bits and a selected one of said sets of said least significant address bits;
and
accessing in a second mode a selected gun portion from each of said pixels by presenting said primary address bits and a selected one of said sets of least significant address bits to said first memory to access a corresponding location for storing said selected gun portion and providing corresponding sets of least significant address bits to said second, third and fourth memories by permuting said set of least significant address bits presented to said first memory.

7 more elements

A processing system operating on data words each having first, second, third and fourth portions comprising:

a memory bank comprising:
a first section of memory including a first storage location for storing said first portions of first and second data words and accessible by a first set of least significant address bits, a second storage location for storing said second portions of third and fourth data words and accessible by a second set of least significant address bits, a third storage location for storing said third portions of fifth and sixth data words and accessible by a third set of least significant bits, and a fourth storage location for storing said fourth portions of seventh and eighth data words and accessible by a fourth set of least significant bits;
a second section of memory including a first storage location for storing said fourth portions of said first and second data words and accessible by said first set of least significant address bits, a second storage location for storing said first portion of said third and fourth data words and accessible by said second set of least significant address bits, a third storage location for storing said second portion of said fifth and sixth data words, said third location accessible by said third set of least significant bits, and a fourth storage location for storing said third portion of said seventh and eighth data words and accessible by said fourth set of least significant bits;
a third section of memory including a first storage location for storing said third portion of said first and second data words and accessible by said first set of least significant address bits, a second storage location for storing said fourth portion of said third and fourth data words and accessible by said second set of least significant address bits, a third storage location for storing said first portion of said fifth and sixth data words and accessible by said third set of least significant bits, and a fourth storage location for storing said second portion of said seventh and eighth data words and accessible by said fourth set of least significant bits;
a fourth section of memory including a first storage location for storing said second portion of said first and second data words and accessible by said first set of least significant address bits, a second storage location for storing said third portion of said third and fourth data words and accessible by said second set of least significant address bits, a third storage location for storing said fourth portion of said fifth and sixth data words and accessible by said third set of least significant bits, and a fourth storage location for storing said first portion of said seventh and eighth data words and accessible by said fourth set of least significant bits;
and
a control circuitry:
accessing in a first mode a selected pair of data words by presenting each of said first, second, third and fourth memories with a corresponding one of said first, second, third and fourth sets of said least significant address bits;
and
accessing in a second mode a selected portion from each of said data words by presenting a selected one of said first, second, third and fourth sets of least significant address bits to said first memory to access a corresponding location for storing said selected portion and providing corresponding sets of least significant address bits to said second, third and fourth memories by permuting said first set of least significant address bits presented to said first memory.

7 more elements

A method of providing access to data in a processing system operating on data words each having at least first and second ordered portions comprising the steps of:

storing said first ordered portion of a first data word in a first location of a first section of memory accessible by a set of most significant address bits and a first set of least significant address bits;
storing said second ordered portion of the first word in a first location of a second section of memory accessible by the set of most significant address bits and the first set of least significant address bits;
storing said first ordered portion of a second word in a second location of the first section of memory accessible by the set of most significant address bits and the second set of least significant address bits;
storing said second ordered portion of the second word in a second location of the second section of memory accessible by the set of most significant address bits and the second set of least significant address;
in a first mode, accessing a selected one of said first and second words by providing the set of most significant address bits to each of the first and second sections of memory and a corresponding one of the first and second sets of bits least significant address bits to both the first and second sections of memory;
and
in a second mode, accessing a selected one the first and second portions from both of the first and second words by providing the set of most significant address bits to each of the first and second sections of memory and providing a selected one of the first and second sets of least significant address bits to the first section of memory and providing an other one of the first and second sets of least significant address bits to the second section of memory.

4 more elements

Dependencies are inferred from the claim text.