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US 5,398,270 AGranted
Data coincidence detecting circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-il Cho, Ki-ho Shin
Life of this patent
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Abstract
A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.
Claims8
A data coincidence detecting circuit comprising:
- a register having an input and a parallel output for latching input n-bit data and outputting said input n-bit data as output n-bit data;
- a counter for sequentially counting n-bit numbers up to 2.sup.n and outputting said sequentially counted n-bit numbers as counter data;
- a comparator having an output for comparing said latched output n-bit data with a counter data to generate an output coincidence detecting signal, wherein said comparator comprises:
- i) a plurality n of XOR gates, each having an output, for comparing respective signals;
- and
- ii) a logic circuit for activating said data coincidence detecting signal when all of said outputs of said XOR gates are low;
- and
- a mask circuit connected to said comparator output for masking said data coincidence detecting signal during a time period when said latched n-bit data is being serially input to said register, said mask circuit comprising a detecting circuit for detecting said time period and for generating a data load detection signal.
5 more elements
A data coincidence detecting circuit comprising:
- a register having an input and a parallel output for latching n-bit data and outputting said input n-bit data as output n-bit data;
- a counter having an output for sequentially counting n-bit numbers up to 2.sup.n and outputting said sequentially counted n-bit numbers as counter data, said counter including n cascaded T flip flops which are synchronized by a first clock signal, wherein each of said T flip flops comprises:
- i.) a first NAND gate and a first inverter generating a reset signal for resetting an output of said T flip flop;
- ii.) a first transmission gate and a second inverter for transmitting an output of said first inverter in response to a said first clock signal;
- iii.) a second transmission gate for latching an output of a third inverter which inverts an output of said first NAND gate and transmitting a result to an input of said first NAND gate;
- and
- iv.) a third transmission gate for latching an output of a fourth inverter which inverts an output of said second inverter in response to a second clock signal, said second clock signal being an inversion of said first clock signal, and transmitting a result to an input of said second inverter;
- a comparator having an output for comparing said latched output n-bit data with some of said counter data to generate an output coincidence detecting signal;
- a mask circuit connected to said comparator output for masking a data coincidence detecting signal during a time period when said latched n-bit data is being serially input to said register, said mask circuit comprising a detecting circuit for detecting said time period and for generating a data load detection signal.
6 more elements
A data coincidence detecting circuit comprising:
- storing means for storing a first n-bits of data and having a serial data load time period beginning at a start of loading and ending at a conclusion of loading said n-bits of data into said storing means;
- a counter having an output for sequentially counting n-bit numbers up to 2.sup.n and outputting said sequentially counted n-bit numbers as counter data, said counting means including n cascaded T flip flops which are synchronized by a first clock signal, wherein each of said T flip flops comprises:
- i.) a first NAND gate and a first inverter generating a reset signal for resetting an output of said T flip flop;
- ii.) a first transmission gate and a second inverter for transmitting an output of said first inverter in response to a said first clock signal;
- iii.) a second transmission gate for latching an output of a third inverter which inverts an output of said first NAND gate and transmitting a result to an input of said first NAND gate;
- and
- iv.) a third transmission gate for latching an output of a fourth inverter which inverts an output of said second inverter in response to a second clock signal, said second clock signal being an inversion of said first clock signal, and transmitting a result to an input of said second inverter;
- comparing means for comparing said n-bits of data to said n-bit numbers and generating a coincidence signal when said n-bits of data is equal to said n-bit number;
- and
- suppression means for suppressing an external output of said coincidence signals generated during said serially loaded data load time period.
7 more elements
Dependencies are inferred from the claim text.