Autonomous pulse train timing controls for time-mark alignment

A digital phase lock loop for making both coarse and fine resolution phase corrections between an incoming clock signal and a sample clock signal, the phase corrections being dispersed over time, said digital phase lock loop comprising:

• a programmable divider circuit having a divisor n that is selectively incrementable or decrementable, coupled to the incoming clock signal for dividing the incoming clock signal and generating a bit clock signal therefrom;
• a divider circuit coupled to the bit clock signal for dividing the bit clock signal and generating the sample clock signal therefrom;
• a phase comparator coupled to the incoming clock signal, the bit clock signal, and the sample clock signal, for measuring a number of the incoming clock signal cycles from a predetermined edge of a time-mark signal when a valid time-mark signal is received, to a predetermined edge of the sample clock signal and for providing a correction signal indicative of a direction and magnitude of a phase error between the sample clock signal and the time-mark signal, the correction signal having a duration proportional to the number of incoming clock signal cycles measured;
• a mode control circuit coupled to a time-mark validated windowing circuit for receiving the valid time-mark signal, said mode control circuit also coupled to the phase comparator for receiving the correction signal and coupled to the programmable divider circuit for receiving the bit clock signal for generating a divide control signal therefrom to control said programmable divider circuit for incrementing or decrementing the divisor n according to the correction signal when the valid time-mark signal is received;
• the time-mark validated windowing circuit coupled to a programmable delay circuit for receiving therefrom a delayed time-mark signal for determining whether the time-mark signal has been received by the time-mark validated windowing circuit within a predetermined time window, and for generating the valid time-mark signal, when the time-mark signal has been received with the predetermined time window and further coupled to the mode control circuit and to the phase comparator for sending the valid time-mark signal thereto;
• and
• the programmable delay circuit coupled to the time-mark signal and to a delay set signal for receiving the time-mark signal and the delay set signal for fine tuning the time-mark signal said programmable delay circuit providing the delayed time-mark signal therefrom.

A remote site transmitter for use in a simulcast transmission system, said remote site transmitter receiving a message bundle from a central controller via an interconnect link, the message bundle including a digital message portion and a launch time, said remote site transmitter converting the digital message portion into an analog message and retransmitting the analog message to a given geographical area at a time determined, at least in part, by the launch time, said remote site transmitter comprising:

• a processor for separating the message bundle into the digital message portion and the launch time, the processor including a phase comparator;
• a receiver for receiving a timing reference signal and generating therefrom a time-mark signal for delivery to the processor;
• a digital to analog converter coupled to the processor for receiving the digital message portion and reconstructing the analog message;
• and
• a transmitter coupled to the digital to analog converter for receiving the analog message and retransmitting the analog message to the given geographical area;
• and
• a clock generator coupled to said phase comparator for making phase corrections on a sample clock signal based on a precision timing signal, the phase corrections being dispersed over time, said clock generator comprising:
• a first divider circuit having a divisor n, coupled to the precision timing signal for dividing the precision timing signal by n to produce a bit clock signal, and coupled to the digital to analog converter and to the processor for providing the bit clock signal thereto;
• a second divider circuit coupled to the bit clock signal for dividing the bit clock signal to produce the sample clock signal, and coupled to the digital to analog converter and to the processor for providing the sample clock signal thereto;
• the phase comparator coupled to the time-mark signal and coupled to the sample clock signal for comparing said time-mark signal and said sample clock signal to generate a correction signal indicating a direction of a phase error, the correction signal having a duration proportional to a number of cycles of the precision timing signal from a predetermined edge of the time-mark signal to a predetermined edge of the sample clock signal for further indicating a magnitude of said phase error between the sample clock signal and the time-mark signal, the correction signal utilized for determining a divide control signal for selectively incrementing or decrementing the divisor n for correcting said phase error simultaneously with the processing of the message bundle.