Circuit for testing circuit blocks controlled by microinstructions

A test circuit for testing circuit blocks controlled with microinstructions, comprising:

• (a) storage means for storing said microinstructions;
• (b) holding means for holding a microinstruction read out of said storage means, said holding means permitting the microinstruction to be set in said holding means from the outside;
• (c) decoding means for decoding control signal data held in said holding means;
• (d) circuit blocks controlled with decoded signals decoded by said decoding means;
• (e) masking means for enabling and disabling a signal read out of said holding means and supplied to said decoding means in synchronism with a test control signal for masking said microinstruction;
• and
• (f) signal generating means for generating signals for enabling and disabling the circuit blocks tested and circuit elements used in the testing of the circuit blocks.

A test circuit for testing a plurality of macro blocks, comprising:

• a micro read only memory for storing a plurality of microinstructions to control the macro blocks;
• a microinstruction register, including flipflops connected in series to form a scan chain, for holding at least one of said microinstructions read out of said micro read only memory under a normal mode and a microinstruction set therein through said scan chain under a first test mode;
• a microdecoder coupled with said register for decoding a microinstruction output of said register and sending a control signal to said macro blocks to control operation of said macro blocks;
• a masking circuit connected between said register and said micro decoder for selectively releasing the contents of said register from a masking condition;
• an inner bus, data pins and address pins through which data is inputted and outputted to and from said macro blocks;
• gate circuits provided between said macro blocks and said bus in order to control input/output of said macro blocks;
• and
• a mask signal generator for generating a mask signal according to an external test sequence control signal and sending said mask signal to said masking circuit.

A semiconductor integrated circuit comprising:

• a micro read only memory for storing microinstructions,
• a microinstruction register for holding at least one microinstruction,
• a microdecoder connected to said microinstruction register for decoding the microinstruction held in said microinstruction register to generate control signals for executing the microinstruction,
• a macro block for carrying out logic operations in accordance with said control signals by exchanging data through a bus;
• and
• a test circuit for testing said macro block when a test sequence control signal is given, said test circuit including:
• a mask circuit connected between said micro instruction register and said microdecoder for masking the microinstruction held in said microinstruction register from said microdecoder;
• a mask signal generator connected to said mask circuit in order to output a mask signal when said test sequence control signal is given, said mask circuit masking the microinstruction held in said microinstruction register in response to said mask signal and freely passing the microinstruction held in said microinstruction register when said test sequence control signal is not given;
• means for outputting test data onto said bus;
• and
• a test enabling signal generating circuit for generating test enabling signals when said test sequence control signal is given, said test enabling signals controlling said test data outputting means to output test data onto said bus.