Packet processing method and apparatus

A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol and including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of

• receiving successive data packets from a data source channel,
• storing non-contiguous portions of the header of each data packet in a high speed data cache memory,
• storing at least said remainder portion of said each data packet in a slower speed memory,
• selecting portions of said header of said each data packet for storage in said high speed data cache memory depending upon the address in the slower speed memory into which an associated remainder portion is stored,
• identifying, from an address in the slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which the selected portion corresponding to said associated remainder portion is stored,
• accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, said accessing step comprising
• providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor,
• reading said stored header directly from said high speed data cache memory by said processor, and
• writing to said high speed data cache memory from said processor for modifying said header, and
• forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of the data packet.

An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising

• means for receiving successive data packets from a data source channel,
• a high speed data cache memory,
• a slower speed memory,
• means for storing at least a portion of said header of each data packet in said high speed data cache memory,
• means for storing at least said remainder portion of said each data packet in said slower speed memory,
• means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of the data packet, and
• means for forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said data packet.

An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising

• means for receiving successive data packets from a data source channel,
• a multi-port high speed data cache memory,
• means for connecting said high speed data cache memory to an input/output data bus and a CPU based processor,
• a slower speed memory,
• means for storing non-contiguous portions of said header of each data packet in said high speed data cache memory,
• means for storing at least said remainder portion of said each data packet in said slower speed memory,
• means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored,
• means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said data packet, said accessing means having
• means for identifying from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored,
• means for reading said stored header directly from said high speed data cache memory by said processor, and
• means for writing to said high speed data cache memory from said processor for modifying said header, and
• means for forwarding a new data packet to a next data packet destination based on the protocol and destination processing of said data packet.