US 5,398,244 A · Method and apparatus for reduced latency in hold bus cycles

Abstract

An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined criteria which indicates that a low latency response is requested. Upon assertion of a QHOLD signal, the CPU issues a burst last signal to prematurely terminate outstanding burst transactions on the bus in a manner transparent to the slave devices. Once the outstanding bus cycles are complete, the CPU performs an internal backoff to immediately release the bus for access by the slave device requesting access. Any pending burst cycles which were terminated prematurely by the QHOLD signal, are subsequently restarted for the data not transacted by the CPU after the slave device completes access to the bus. The internal backoff mechanism is similarly transparent to the slave devices and does not cause a backoff signal to be issued to the peripherals or devices coupled to the bus. Thus, the addition of a quick hold protocol is added without significant modification of the slave devices' bus interface.

Claims29

Dependent claims

A system comprising:

a bus;
a master device coupled to the bus, said master device having priority of access to the bus and issuing burst addresses for data operations wherein in response to a burst address, a plurality of data cycles transferring data are executed to complete the burst transaction and bus cycle;
at least one slave device coupled to the bus, said slave device gaining access to the bus by issuing a bus request and receiving a bus grant signal;
a bus arbiter coupled to a bus, said arbiter arbitrating device access to the bus according to bus requests received, said bus arbiter issuing a QHOLD signal to the master device when a slave device requests access to the bus;
said master device, upon receipt of the QHOLD signal, if burst addresses have been issued on the bus and burst transactions are incomplete, issuing a BLAST# signal indicating to said at least one slave device coupled to the bus that the burst transaction is complete, executing an internal backoff to release the bus once the bus cycles are complete and issuing a QHLDA signal to the arbiter indicating that the QHOLD request is acknowledged and the slave device can have access to the bus;
wherein the arbiter issues a bus grant signal to the slave device and the slave device quickly gains access to the bus.

3 more elements

A bus system for interconnecting a plurality of devices via a bus, said system comprising:

an arbiter coupled to the bus for arbitrating requests for access to the bus by the plurality of devices, said arbiter comprising means for issuing a first hold signal "QHOLD" to a device currently accessing the bus when another device issues a request to access the bus;
a master device comprising;
means for initiating bus burst cycles by issuing a burst address on the bus to a slave device, said slave device responding by providing a plurality of data elements located at sequential addresses to the burst address, and
means responsive to the QHOLD signal comprising;
means for issuing a burst last signal "BLAST#" on the bus for burst cycles outstanding on the bus, said BLAST# signal prematurely terminating a burst cycle by notifying the slave device that the last data element provided completes the burst cycle, thereby decreasing the latency incurred until the end of the bus cycle is reached,
means for executing an internal backoff of the master device from the bus, said means for executing an internal backoff receiving the QHOLD signal and executing the internal backoff once outstanding bus cycles are complete, and
means for issuing a first hold acknowledge "QHLDA" signal to the arbiter to notify the arbiter that the bus is released for access by the requesting device;
wherein the bus is released for access by the master device with the minimal of latency in a manner transparent to the slave devices.

5 more elements

In a system comprising a master device, at least one slave device and a bus arbiter coupled to a bus, said arbiter arbitrating device access to the bus, said master device having priority of access to the bus, a process for quickly providing bus access to slave devices, comprising the steps of:

(a) selectively issuing a first hold "QHOLD" signal to the master device;
(b) upon receipt of the QHOLD signal;
if at least one burst transaction is pending on the bus, then
(i) issuing a burst last "BLAST#" signal to indicate to the slave devices that the burst cycle is complete, said BLAST# signal functioning to prematurely terminate access to the bus, and
(ii) issuing a first hold acknowledge "QHLDA" signal to the arbiter;
(c) when outstanding bus cycles are complete, issuing an internal backoff signal within the master device, said internal backoff signal causing said master device to release the bus;
and
(d) upon receipt of the QHLDA signal, said arbiter granting the slave device ownership of the bus;
(e) wherein bus ownership by the master device is quickly released.

6 more elements

Dependencies are inferred from the claim text.

Method and apparatus for reduced latency in hold bus cycles

Life of this patent

Method and apparatus for reduced latency in hold bus cycles

Life of this patent

Abstract

Claims29