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US 5,398,213 AGranted
Access time speed-up circuit for a semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsEung-Moon Yeon, Young-Ho Lim
Life of this patent
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Abstract
A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.
Claims2
A semiconductor memory device which operates in a page mode comprising:
- a memory cell array including a plurality of memory cells, each cell having a normal address, said memory cell array further being divided into a plurality of pages, each page being defined by a page address that represents a plurality of said memory cells;
- means for sensing data associated with first and second normal addresses;
- and
- first and second latch circuit arrays for outputting data corresponding to said first normal address when said means for sensing is sensing data corresponding to said second normal address, said first and second latch circuit arrays alternatively activated by a latch control signal generated in response to a change in said normal address.
1 more element
Dependencies are inferred from the claim text.