Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n <2.sup.n +m<2.sup.n+1 ;
• top address storing means for storing a top address signal of (n+1) bits;
• address converting means for receiving an address signal of (n+1) bits and the top address signal and for converting the address signal into an internal address signal of (n+1) bits in accordance with the top address signal;
• decoding means for receiving the internal address signal and for specifying one of the (2.sup.n +m) memory cells in accordance with the internal address signal;
• output means for outputting data stored in the memory cell specified by the decoding means;
• empty address detecting means for receiving at least two bits of the internal address signal of (n+1) bits and for generating a detection signal which indicates whether the address signal represents an empty address or not;
• and
• control means for receiving an enable signal and for generating a control signal for outputting the data stored in the specified memory cell in accordance with the enable signal,
• wherein the control means further receives the detection signal and generates a control signal for inhibiting the data from being output when the address signal specifies an empty address, regardless of the state of the enable signal.

A semiconductor memory device comprising:

• a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n <2.sup.n +m<2.sup.n+1 ;
• address converting means for receiving an address signal of (n+1) bits and for outputting an address signal for accessing one of the (2.sup.n +m) memory cells in accordance with the address signal;
• decoding means for receiving the address signal from the address converting means and for specifying one of the (2.sup.n +m) memory cells in accordance with the address signal;
• output means for outputting data stored in the memory cell specified by the decoding means;
• and
• empty address detecting means for receiving at least two bits of the address signal of (n+1) bits and for generating a detection signal which indicates whether the address signal represents an empty address or not,
• wherein the address converting means converts the received address signal into an address signal for allowing access to one of the (2.sup.n +m) memory cells when the address signal represents an empty address.