Structure and method for providing prioritized arbitration in a dual port memory
AssigneeIntegrated Device Technology, Inc.
InventorsAvigdor Willenz, Kelly A. Maas
Life of this patent
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Abstract
An integrated circuit dual port memory provides a preferred port which is always granted priority of memory access when memory access requests arrive simultaneous from both ports of the dual port memory. To implement this priority scheme, the memory request signal from the preferred port controls a multiplexor to select the input signals from the preferred port over the input signals from the non-preferred port. The memory request signal from the preferred port also serves as a busy signal to block a simultaneous memory access by the non-preferred port. In one embodiment, memory request signals of both ports are latched into registers clocked by the same clock signal.
Claims10
A dual port memory, comprising:
- a memory element addressable by address signals for storing data;
- a first port receiving (i) a first set of address signals for accessing said memory element, and (ii) a first memory request signal for indicating a pending memory access from said first port;
- a second port receiving (i) a second set of address signals for accessing said memory element, (ii) a second memory request signal for indicating a pending memory access from said second port, and (iii) said first memory request signal, said second port providing said first memory request signal as a busy signal to indicate that, when said first memory request signal is asserted, said second port is temporarily unavailable;
- and
- a multiplexer controlled by said first memory request signal for selecting one of said first and second sets of address signals for accessing said memory element.
A method for providing a dual port memory, comprising the steps of:
- providing a memory element addressable by address signals for storing data;
- providing a first port receiving (i) a first set of address signals for accessing said memory element, and (ii) a first memory request signal for indicating a pending memory access from said first port;
- providing a second port receiving (i) a second set of address signals for accessing said memory element, (ii) a second memory request signal for indicating a pending memory access from said second port, and (iii) said first memory request signal, said second port providing said first memory request signal as a busy signal to indicate that, when said first memory request signal is asserted, said second port is temporarily unavailable;
- and
- providing a multiplexer controlled by said first memory request signal for selecting one of said first and second sets of address signals for accessing said memory element.
Dependencies are inferred from the claim text.