Semiconductor memory device having memory cells reorganizable into memory cell blocks different in size
AssigneeNEC Corporation
InventorMisao Higuchi
Life of this patent
Estimating the term…
Abstract
An electrically erasable and programmable read only memory device stores pieces of organizing information in a block organizer after completion of a process of fabricating thereof for producing organizing signals, and a row address decoder and driver unit assumes memory cell blocks to be reorganized into virtual memory cell blocks in response to the organizing signals so that user can freely reorganize the memory cell blocks.
Claims9
A semiconductor memory device comprising:
- a) a memory cell array having a plurality of memory cell blocks each implemented by a plurality of addressable memory cells;
- b) a block organizer storing pieces of organizing information in a non-volatile manner after completion of a process of fabricating said semiconductor memory device, and producing organizing signals indicative of an arrangement of virtual memory cell blocks formed from said plurality of memory cell blocks;
- c) a first address decoder means responsive to said organizing signals for assuming selected one or ones of said plurality of memory cell blocks to be one of said virtual memory cell blocks, said first address decoder circuit being further responsive to external address bits for selecting the addressable memory cells from said one of said virtual memory cell blocks;
- and
- d) a second address decoder means responsive to other external address bits for selectively coupling said addressable memory cells with an interface.
An electrically erasable and programmable read only memory device fabricated on a semiconductor chip and selectively entering into a programming mode for storing pieces of organizing information and a standard mode for erasing data bits, writing new data bits and reading out said new data bits, comprising:
- a) a memory cell array having a plurality of memory cell blocks each implemented by a plurality of memory cells arranged in rows and columns for storing said data bits and said new data bits;
- b) an address buffer unit supplied with external address bits for producing first internal address signals in said standard mode and other external address bits for producing second internal address signals in said programming mode;
- c) a block organizer having
- c-1) a first decoder circuit for producing decoded signals from said second internal address signals in said programming mode,
- c-2) a plurality of non-volatile memory circuits coupled with said first decoder circuit, said decoded signal sequentially enabling said plurality of non-volatile memory circuits for storing said pieces of organizing information, and
- c-3) a second decoder circuit operative to produce a plurality of organizing signals from said pieces of organizing information in said standard mode;
- d) a row address decoder and driver unit responsive to said plurality of organizing signals for organizing said plurality of memory cell blocks into virtual memory cell blocks, said row address decoder and driver unit being further responsive to predetermined first internal address signals selected from said first internal address signals for sequentially selecting all of the rows of memory cells incorporated in one of said virtual memory cell blocks in said standard mode;
- e) a column address decoder and selector unit responsive to other predetermined first internal address signals selected from said first internal address signals for sequentially selecting memory cells from said memory cells incorporated in said one of said virtual memory cell blocks in said standard mode;
- f) a write-in and sense amplifying unit for transferring said new data bits between said column address decoder and selector unit and an input and output buffer unit in said standard mode;
- and
- g) a voltage generator connectable with source nodes of said memory cells incorporated in one of said plurality of virtual memory cell blocks for erasing said data bits in said standard mode.
Dependencies are inferred from the claim text.