Serial access memory with column address counter and pointers
AssigneeOki Electric Industry Co., Ltd.
InventorsIturou Iwakiri, Koji Murakami
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Abstract
A serial access memory has multiple memory blocks, each with a row-and-column array of memory cells for storing data. Data access is synchronized with a clock signal. A column address counter counts the clock signal to generate a column address. A block selector decodes upper bits of the column address to generate a series of block select signals, which are distributed to the memory blocks. In each memory block a shift register receives and shifts one block select signal to generate a series of column select signals.
Claims18
A method of selecting successive columns in successive memory blocks in a serial access memory, each of the successive memory blocks having shift registers which select the columns respectively, the method comprising the steps of:
- (a) counting a clock signal to generate column address signals;
- (b) decoding said column address signals to generate a series of block select signals selecting respective memory blocks;
- (c) applying one of said block select signals to one of said memory blocks and shifting said block signal through a corresponding one of said respective shift registers in synchronization with said clock signal, thereby selecting successive columns in said memory block;
- and
- (d) applying another one of said block select signals to another one of said memory blocks and shifting said another block select signal through another corresponding one of said shift registers in synchronization with said clock signal after step (c), thereby selecting successive columns in said another memory block.
A serial access memory for accessing data in synchronization with a clock signal, comprising:
- a column address counter for counting said clock signal to generate column address signals;
- a block selector coupled to decode said column address signals and thereby generating a series of block select signals;
- and
- a plurality of memory blocks having respective memory cell arrays for storing data in rows and columns, and respective shift registers clocked by said clock signal, each of said shift registers being coupled to receive and shift a different one of said block select signals in response to said clock signal and thereby generating a series of column select signals to select successive columns in its memory block.
A serial access memory having first and second memory blocks, said memory comprising:
- a column address counter for counting a clock signal to produce a plurality of column address signals;
- a block selector coupled to decode said column address signals and producing a first block select signal and a second block select signal after the first block select signal is produced;
- wherein said first memory block has a first memory cell array for storing data in rows and columns and a first pointer substantially arranged on a lateral side of said first memory block, said first pointer receiving and shifting the first block select signal therein in response to the clock signal and selecting successive columns in the first memory cell array in response to the shifted first block select signal;
- and
- wherein said second memory block is arranged laterally adjacent to said first memory block on a side opposite of said first pointer, said second memory block having a second memory cell array for storing data in rows and columns and a second pointer substantially arranged on a lateral side of said second memory block being adjacent to said first memory block, said second pointer receiving and shifting the second block select signal therein in response to the clock signal and selecting successive columns in the second memory cell array in response to the shifted second block select signal.
Dependencies are inferred from the claim text.