MOS random access memory device with an internal voltage-down converting transistor

A dynamic random access memory comprising:

• a semiconductor substrate;
• a memory cell array section including a plurality of memory cells which have data storage elements and transfer-gate transistors respectively;
• parallel bit lines associated with said memory cell array section;
• parallel word lines formed transverse to said bit lines and connected to said transfer-gate transistors of said memory cells;
• a word-line driver circuit connected to said word lines;
• a restoring circuit connected to said bit lines;
• first means for providing said word-line driver circuit with a first voltage which is potentially higher than a power supply voltage externally supplied to said dynamic random access memory;
• and
• second means, connected to said restoring circuit, for providing said restoring circuit with a second voltage which is potentially lower than said power supply voltage, said second means including a transistor having substantially the same threshold voltage as that of said transfer-gate transistors and a gate electrode coupled to said first means.

A dynamic random access memory system comprising:

• a memory cell array section including a plurality of memory cells each of which has a data storage element and a transfer-gate transistor with a control gate electrode;
• parallel bit lines associated with said memory cell array section, said parallel bit lines including a bit line pair;
• parallel word lines formed transverse to said parallel bit lines, including a word line connected to said control gate electrode of said transfer-gate transistor;
• booster circuit means supplied with a power supply voltage, for providing a potentially raised voltage which is higher than said power supply voltage;
• a sense amplifier circuit associated with said bit line pair;
• a word-line driver circuit having an input terminal connected to said booster circuit means and an output terminal connected to said word line;
• and
• a restoring circuit connected to said sense amplifier circuit, said restoring circuit including a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate electrode connected to said booster circuit means, a drain electrode supplied with said power supply voltage, and a source electrode whereat a potentially decreased voltage appears which is lower than said power supply voltage, said voltage-down converting transistor having substantially the same threshold voltage as that of said transfer-gate transistor.