Memory programming load-line circuit with dual slope I-V curve

A nonvolatile memory comprising:

• (a) a memory array that includes a first memory cell coupled to a first bit line, a second memory cell coupled to a second bit line, a third memory cell coupled to a third bit line, and a fourth memory cell coupled to a fourth bit line, the memory array further comprising a first programming load line circuit and a second programming load line circuit, wherein the first load line circuit is selectively coupled to the first bit line and the second bit line such that at most one of the first and second bit lines can be selected for programming, wherein the second programming load line circuit is selectively coupled to the third and fourth bit lines such that at most one of the third and fourth bit lines can be selected for programming, wherein the first memory cell receives a first current during programming of the first memory cell, wherein the second memory cell receives a second current during programming of the second memory cell, the third memory cell receives a third current during programming of the third memory cell, the fourth memory cell receives a fourth current during programming of the fourth memory cell;
• (b) a first current regulating circuitry coupled to the first programming load line and a second current regulating circuitry coupled to the second programming load line, the first and second current regulating circuitry regulating the first, second, third and fourth currents during programming of the first, second, third and fourth memory cells, wherein when the first cell is being programmed and the third and fourth cells are not being programmed the circuitry limits a first programming load line current flowing through the first programming load line to be substantially equivalent to the first programming load line current if the first and third memory cells are being programmed substantially at the same time.

A nonvolatile memory comprising:

• (a) a memory army that includes a first memory cell coupled to a first bit line, a second memory cell coupled to a second bit line, wherein the first memory cell receives a first current during programming of the first memory cell, wherein the second memory cell receives a second current during programming of the second memory cell, wherein the first memory cell has a first programming voltage when receiving the first current, wherein the second memory cell has a second programming voltage when receiving the second current;
• (b) current regulating circuitry coupled to the array, the circuitry regulating the first and second currents during programming of the first and second memory cells, wherein when the first cell is being programmed and the second cell is not being programmed the circuitry limits the first current flowing through the first bit line for programming the first memory cell to be substantially equivalent to the first current if the first and second memory cells are being programmed substantially at the same time, wherein the current regulating circuitry regulates a first programming voltage-to-first current ratio such that the ratio has a first value when the first programming voltage is between a first potential level and a second potential level and a second value when the first programming voltage is between the second potential level and a third potential level, wherein the first value is substantially not equal to the second value.